LITE5200B User’s Manual, Rev. 2
Index-8
Freescale Semiconductor
overview, 1-33
System linkage instructions, 2-43, A-22
System management interrupt, 4-33, 9-2
System quiesce control signals, 8-41
System register unit
execution timing, 6-22
latency, CR logical instructions, 6-27
latency, system register instructions, 6-27
System status
CKSTP_IN, 7-24
CKSTP_OUT, 7-24
HRESET, 7-25
INT, 7-23
MCP, 7-24
QACK, 7-26
QREQ, 7-26
RSRV, 7-27
SMI, 7-23
SRESET, 7-25
TBEN, 7-27
TLBISYNC, 7-27
T
TA signal, 7-21
Table search operations
algorithm, 5-27
software routines, 5-31
software routines for the 603e, 5-36–5-47
SRR1 bit settings, 4-10
table search flow (primary and secondary), 5-29
TBEN signal, 7-27
TBST signal, 7-12, 8-13, 8-23
TC
n
signals, 7-13, 8-19
TEA signal, 7-22, 8-27
Termination, 8-19, 8-24
TGPR0–GPR3 registers, 5-32
Throughput, 6-3
Timing diagrams, interface
address transfer signals, 8-11
burst transfers with data delays, 8-35
single-beat reads, 8-31
single-beat reads with data delays, 8-33
single-beat writes, 8-32
single-beat writes with data delays, 8-34
use of TEA, 8-36
using DBWO, 8-42
Timing, instruction
BPU execution timing, 6-17
branch timing example, 6-20
cache arbitration, 6-10
cache hit, 6-10, 6-12, 6-14
FPU execution timing, 6-21
instruction dispatch, 6-15
instruction flow, 6-8
instruction scheduling guidelines, 6-24
IU execution timing, 6-21
latency summary, 6-26
load/store unit execution timing, 6-22
overview, 6-3
SRU execution timing, 6-22
stage, definition, 6-2
TLB
description, 5-24
invalidate, A-24
invalidate (tlbie instruction), 5-26, 5-47
TLB management instructions, 2-46, A-24
TLBISYNC signal, 7-27
Trace exception, 4-29
Transactions, data cache, 3-8
Transfer, 8-11, 8-23
Trap instructions, 2-37
TS signal, 7-5, 8-11
TSIZ
n
signals, 7-12, 8-13
TT
n
signals, 7-8, 8-12
U
Use of TEA, timing, 8-36
User mode, 4-1
User instruction set architecture (UISA), xxvii, 1-15,
2-1
User-level registers summary, 2-2
Using DBWO, timing, 8-42
V
Virtual environment architecture (VEA), xxvii, 1-15,
2-40
W
WIMG bits, 3-10, 8-29
Write with atomic operation, 3-19
Write with flush operation, 3-19
Write with kill operation, 3-19
Write-back, 6-3
Write-back mode, 3-11
Write-through mode (W bit)
cache interactions, 3-10
timing considerations, 6-23
W-bit setting, 3-11
WT signal, 7-14
X
XATS signal (603-specific), 1-6