LITE5200B User’s Manual, Rev. 2
Glossary-10
Freescale Semiconductor
Shadowing.
Shadowing allows a register to be updated by instructions that are executed
out of order without destroying machine state information.
Signaling NaN.
A type of
NaN
that generates an invalid operation program exception
when it is specified as arithmetic operands. See
Quiet
NaN
.
Significand.
The component of a binary floating-point number that consists of an explicit
or implicit leading bit to the left of its implied binary point and a fraction field to
the right.
Simplified mnemonics.
Assembler mnemonics that represent a more complex form of a
common operation.
Slave.
The device addressed by a master device. The slave is identified in the address
tenure and is responsible for supplying or latching the requested data for the
master during the data tenure.
Snooping.
Monitoring addresses driven by a bus master to detect the need for coherency
actions.
Snoop push.
Response to a snooped transaction that hits a modified cache block. The
cache block is written to memory and made available to the snooping device.
Split
-
transaction.
A transaction with independent request and response tenures.
Split-transaction bus.
A bus that allows address and data transactions from different
processors to occur independently.
Stage.
The term ‘stage’ is used in two different senses, depending on whether the pipeline
is being discussed as a physical entity or a sequence of events. In the latter case, a
stage is an element in the pipeline during which certain actions are performed,
such as decoding the instruction, performing an arithmetic operation, or writing
back the results. Typically, the latency of a stage is one processor clock cycle.
Some events, such as dispatch, write-back, and completion, happen
instantaneously and may be thought to occur at the end of a stage. An instruction
can spend multiple cycles in one stage. An integer multiply, for example, takes
multiple cycles in the execute stage. When this occurs, subsequent instructions
may stall. An instruction may also occupy more than one stage simultaneously,
especially in the sense that a stage can be seen as a physical resource—for
example, when instructions are dispatched they are assigned a place in the CQ at
the same time they are passed to the execute stage. They can be said to occupy
both the complete and execute stages in the same clock cycle.
Stall.
An occurrence when an instruction cannot proceed to the next stage.
Static branch prediction.
Mechanism by which software (for example, compilers) can
hint to the machine hardware about the direction a branch is likely to take.
Superscalar machine.
A machine that can issue multiple instructions concurrently from
a conventional linear instruction stream.
