LITE5200B User’s Manual, Rev. 2
Freescale Semiconductor
Index-3
DBB signal, 7-17, 8-8, 8-22
DBDIS signal, 7-21
DBG signal, 7-17, 8-7
DBWO signal, 7-17, 8-7, 8-23, 8-42
DCMP and ICMP registers, 5-34
Decrementer interrupt, 4-28, 9-2
Defined instruction class, 2-17
DH
n
/DL
n
signals, 7-18
Direct address translation (translation disabled)
data accesses, 3-11, 5-9, 5-11, 5-19
instruction accesses, 3-11, 5-9, 5-11, 5-19
Direct-store access on the 603e, 3-9
Dispatch considerations, 6-15
DMISS and IMISS registers, 5-33
DPE signal, 7-20
DP
n
signals, 7-19
DRTRY signal, 7-22, 8-24, 8-27
DSI exception, 4-20
E
Effective address calculation
address translation, 5-3
branches, 2-20, 2-36
loads and stores, 2-20, 2-30, 2-34
Error termination, 8-27
Exceptions
alignment exception, 4-24
data TLB miss on load, 4-30
data TLB miss on store, 4-31
decrementer interrupt, 4-28
DSI exception, 4-20
enabling and disabling, 4-13
exception classifications, 4-2
exception processing, 4-9, 4-13
external interrupt, 4-23
FP unavailable exception, 4-28
instruction address breakpoint, 4-31
instruction related, 2-21
instruction TLB miss, 4-30
machine check exception, 4-19
overview, 1-26
program exception, 4-26
register settings
FPSCR, 4-27
MSR, 4-16
SRR0/SRR1, 4-10
reset, 4-17
returning from an exception handler, 4-14
summary, 2-21
system call, 4-28
system management interrupt, 4-33
trace exception, 4-29
Execution synchronization, 2-21
Execution units, 1-9
External control instructions, 2-42, 8-18, A-24
F
Features list, 1-3
Finish cycle, definition, 6-2
Floating-point model
FE0/FE1 bits, 4-13
FP arithmetic instructions, 2-26, A-18
FP compare instructions, 2-28, A-19
FP execution models, 2-13
FP load instructions, 2-34, A-21
FP move instructions, 2-29, A-22
FP multiply-add instructions, 2-27, A-18
FP rounding/conversion instructions, 2-27, A-18
FP store instructions, 2-35, A-21
FP unavailable exception, 4-28
FPSCR instructions, 2-28, A-19
Floating-point unit
execution timing, 6-21
latency, FP instructions, 6-29
overview, 1-10
Flow control instructions
branch instruction address calculation, 2-36
branch instructions, 2-36
condition register logical, 2-37
Flush block operation, 3-19
FPR0–FPR31, 2-2
FPSCR instructions, 2-28, A-19
G
GBL signal, 7-14
GPR0–GPR31, 2-2
Guarded memory bit (G bit)
cache interactions, 3-10
G-bit setting, 3-12
H
HASH1 and HASH2 registers, 5-34
Hashing functions
primary PTEG, 5-30
secondary PTEG, 5-31
HID0 (hardware implementation-dependent 0)
registers
nap bit, 9-4
HID0 register
DCFI, DCE, DLOCK bits, 3-6
doze bit, 9-4
DPM enable bit, 9-3
ICFI, ICE, ILOCK bits, 3-4
PID7v-specific bits, 1-19, 3-22
HID1 register
bit settings, 2-10
PLL configuration, 2-10, 7-30