LITE5200B User’s Manual, Rev. 2
Index-6
Freescale Semiconductor
doze, nap, sleep, DPM bits, 2-10
full-power mode, 9-3
nap mode, 9-4
programmable power modes, 9-3
sleep mode, 9-5
software considerations, 9-6
Power management modes, 1-14
Power-on reset settings, 4-17
PowerPC 603-specific features, 1-6
PowerPC architecture
instruction list, A-1, A-8, A-15
levels of implementation, 1-15
operating environment architecture (OEA), xxvii, 1
-15, 2-42
user instruction set architecture (UISA), xxvii,
1-15, 2-1
virtual environment architecture (VEA), xxvii, 1-1
5, 2-40
Privilege levels
supervisor-level cache instruction, 2-44
Privileged state,
see
Supervisor mode
Problem state,
see
User mode
Process switching, 4-15
Processor control instructions, 2-38, 2-40, 2-43, A-23
Processor identification (PID) number definition, 1-1
Program exception, 4-26
Program order, definition, 6-2
Programmable power states
doze mode, 9-3
full-power mode (DPM enabled/disabled), 9-3
nap mode, 9-4
sleep mode, 9-5
Protection of memory areas
no-execute protection, 5-12
options available, 5-10
protection violations, 5-14
PTEGs (PTE groups), 5-27
PTEs (page table entries), 5-27
Q
QACK signal, 7-26, 8-37, 8-40
QREQ signal, 7-26, 8-41
Qualified bus grant, 8-7
Qualified data bus grant, 8-22
R
Read atomic operation, 3-19
Read operation, 3-19
Read with intent to modify operation, 3-19
Real address (RA),
see
Physical address generation
Real addressing mode,
see
Direct address translation
Reduced-pinout mode, 8-39
Referenced (R) bit maintenance
recording, 5-11, 5-21–5-23, 5-29
Registers
configuration registers
MSR, 2-4
PVR, 2-4
exception handling registers
DAR, 2-5
DSISR, 2-5
SPRG0–SPRG3, 2-5
SRR0, 2-5
SRR1, 2-5
implementation-specific registers
DCMP/ICMP, 2-10
DMISS/IMISS, 2-10
HASH1/HASH2, 2-11
HID0/HID1, 1-19, 2-6
IABR, 2-12
RPA, 2-12
Run_N, 1-19
memory management registers
BAT, 2-5
SDR1, 2-5
SR, 2-5
supervisor-level
BAT, 2-5
DAR, 2-5
DCMP and ICMP, 2-10, 5-34
DEC, 2-6
DMISS and IMISS, 2-10, 5-33
DSISR, 2-5
EAR, 2-6
HASH1 and HASH2, 2-11, 5-34
HID0 and HID1, 1-19, 2-6
IABR, 2-12
MSR, 2-4
PVR, 2-4
RPA, 2-12
SDR1, 2-5
SPRG0–SPRG3, 2-5
SR, 2-5
SRR0, 2-5
SRR1, 2-5
TB, 2-6
user-level
CR, 2-2
CTR, 2-4
FPR0–FPR31, 2-2
FPSCR, 2-2
GPR0–GPR31, 2-2
LR, 2-4
TB, 2-4
TGPR0–TGPR3, 5-32
XER, 2-4
Rename buffer, 6-2