Abatron Configuration File
LITE5200B User’s Manual, Rev. 0
A-2
Freescale Semiconductor
TSZ4 0x000000000x07FFFFFF ;SDRAM CS0, 128 MByte
MMAP 0x000000000x07FFFFFF ;SDRAM CS0,1, 80 MByte
WM32 0x80000B00 0x80000000 ;GPIO Enable CS1
; init SDRAM controller for DDR 132MHz, CL=2.5
WM32 0x80000108 0x93733A30 ; SDRAM Config 1
; srd2rwp = 9 ( )
; swt2rwp = 3 ( this is recommended value for DDR )
; rd_latency = 7 ( CAS = 2.5 )
; act2rw = 3 ( suggested value for DDR is 0x2 )
; pre2act = 3 ( recommended value at 132MHz is 0x2 )
; ref2ac = 0xA
; wr_latency = 3
; single read2readwrite delay cl=2.5, swt2rp =3 for DDR,
read CAS = 7 (cl=2,5), act2rd= 2,66 -> 3, pre2act=2,66 -> 3, refresh to no read
delay=0xA, Write latency for DDR =3
WM32 0x8000010C 0x45770000 ;SDRAM Config 2
WM32 0x80000104 0xF14F0F00 ;SDRAM Control: Mode register write enablemode reg=0, clk
enable=1, DDR mode, auto refresh enabled, hi_addr set, use A10 for precharge, drive
rule=1, refresh interval=d15, dqs_oe=b1111
WM32 0x80000104 0xF14F0F02 ;SDRAM Control: Mode register write enable, precharge all
WM32 0x80000100 0x40090000 ;SDRAM Extended Mode DLL enabled, drive strength reduced,
QFC disabled
WM32 0x80000100 0x058D0000 ;SDRAM Mode, reset DLLburst 8, sequential, CAS latency
2.5
WM32 0x80000104 0xF14F0F02 ;SDRAM Control: precharge all
WM32 0x80000104 0xF14F0F04 ;SDRAM Control: refresh
WM32 0x80000100 0x018D0000 ;SDRAM Mode, normal DLL operation
WM32 0x80000104 0x714F0F00 ;SDRAM Control, lock Mode register
MMAP 0x80000000 0x80003FFF ;Memory map for Internal Register
MMAP 0x80008000 0x8000BFFF ;Memory map for On-chip SRAM