CHAPTER 21 CLOCK MONITOR
User’s Manual U16899EJ2V0UD
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Figure 21-3. Timing of Clock Monitor (3/4)
(5) Clock monitor status after STOP mode is released
(CLME = 1 is set when CPU clock operates on Ring-OSC clock and before entering STOP mode)
Clock monitor status
Monitoring
Monitoring
stopped
Monitoring stopped
Monitoring
CLME
Ring-OSC clock
(CPU clock)
High-speed system clock
CPU operation
Normal
operation
17 clocks
Clock supply
stopped
Normal operation
Oscillation
stopped
Oscillation stabilization time
(time set by OSTS register)
STOP
When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before entering STOP mode, monitoring
automatically starts at the end of the high-speed system clock oscillation stabilization time. Monitoring is stopped in
STOP mode and during the oscillation stabilization time.
(6) Clock monitor status after high-speed system clock oscillation is stopped by software
Clock monitor status
CLME
MSTOP or
MCC
Note
Ring-OSC clock
High-speed system clock
Oscillation stabilization time
(time set by OSTS register)
Normal operation (Ring-OSC clock or subsystem clock
Note
)
Monitoring
Monitoring
stopped
Monitoring
CPU operation
Monitoring stopped
Oscillation
stopped
When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before or while oscillation of the high-
speed system clock is stopped, monitoring automatically starts at the end of the high-speed system clock oscillation
stabilization time. Monitoring is stopped when oscillation of the high-speed system clock is stopped and during the
oscillation stabilization time.
Note The register that controls oscillation of the high-speed system clock differs depending on the type of the
clock supplied to the CPU.
•
When CPU operates on Ring-OSC clock: Controlled by bit 7 (MSTOP) of the main OSC control
register (MOC)
•
When CPU operates on subsystem clock: Controlled by bit 7 (MCC) of the processor clock control
register (PCC)
