APPENDIX D LIST OF CAUTIONS
User’s Manual U16899EJ2V0UD
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Chapter
Cl
assi
fi
cati
on
Function Details
of
Function
Cautions Page
The OVF0n flag is also set to 1 in the following case.
When any of the following modes is selected: the mode in which clear & start
occurs on a match between TM0n and CR00n, the mode in which clear & start
occurs at the TI00n valid edge, or the free-running mode
→
CR00n is set to FFFFH
→
TM0n is counted up from FFFFH to 0000H.
p. 178
OVF0n flag
operation
Even if the OVF0n flag is cleared before the next count clock is counted (before
TM0n becomes 0001H) after the occurrence of TM0n overflow, the OVF0n flag is
re-set newly so this clear is not valid.
p. 178
Conflict
operation
When a read period of the 16-bit timer capture/compare register (CR00n/CR01n)
and a capture trigger input (CR00n/CR01n used as capture register) conflict, the
priority is given to the capture trigger input. The data read from CR00n/CR01n is
undefined.
p. 178
Soft
Even if 16-bit timer counter 0n (TM0n) is read, the value is not captured by 16-bit
timer capture/compare register 01n (CR01n).
p. 179
Regardless of the CPU’s operation mode, when the timer stops, the input signals
to the TI00n/TI01n pins are not acknowledged.
p. 179
Timer operation
The one-shot pulse output mode operates correctly only in the free-running mode
and the mode in which clear & start occurs at the TI00n valid edge. In the mode
in which clear & start occurs on a match between the TM0n register and CR00n
register, one-shot pulse output is not possible because an overflow does not
occur.
p. 179
If the TI00n pin valid edge is specified as the count clock, a capture operation by
the capture register specified as the trigger for the TI00n pin is not possible.
p. 179
To ensure the reliability of the capture operation, the capture trigger requires a
pulse longer than two cycles of the count clock selected by prescaler mode
register 0n (PRM0n).
p. 179
Capture
operation
The capture operation is performed at the falling edge of the count clock. An
interrupt request input (INTTM00n/INTTM01n), however, is generated at the rise
of the next count clock.
p. 179
Compare
operation
A capture operation may not be performed for CR00n/CR01n set in compare
mode even if a capture trigger has been input.
p. 179
If the TI00n or TI01n pin is high level immediately after system reset and the rising
edge or both the rising and falling edges are specified as the valid edge of the
TI00n or TI01n pin to enable the 16-bit timer counter 0n (TM0n) operation, a rising
edge is detected immediately after the operation is enabled. Be careful therefore
when pulling up the TI00n or TI01n pin. However, if the TI00n or TI01n pin is high
level when re-enabling operation after the operation has been stopped, the rising
edge is not detected.
p. 179
Chapter 6
Hard
16-bit
timer/
event
counters
00, 01
(TM00,
TM01)
Edge detection
The sampling clock used to remove noise differs when the TI00n pin valid edge is
used as the count clock and when it is used as a capture trigger. In the former
case, the count clock is f
X
, and in the latter case the count clock is selected by
prescaler mode register 0n (PRM0n). The capture operation is started only after
a valid edge is detected twice by sampling, thus eliminating noise with a short
pulse width.
p. 179
