APPENDIX D LIST OF CAUTIONS
User’s Manual U16899EJ2V0UD
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Chapter
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Function Details
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Function
Cautions Page
Timer operation must be stopped before setting CRC00.
p. 145
Soft
When the mode in which clear & start occurs on a match between TM00 and
CR000 is selected with 16-bit timer mode control register 00 (TMC00), CR000
should not be specified as a capture register.
p. 145
Hard
CRC00:
Capture/
compare control
register 00
To ensure that the capture operation is performed properly, the capture trigger
requires a pulse longer than two cycles of the count clock selected by prescaler
mode register 00 (PRM00).
p. 145
Timer operation must be stopped before setting CRC01.
p. 146
Soft
When the mode in which clear & start occurs on a match between TM01 and
CR001 is selected with 16-bit timer mode control register 01 (TMC01), CR001
should not be specified as a capture register.
p. 146
Hard
CRC01:
Capture/
compare control
register 01
To ensure that the capture operation is performed properly, the capture trigger
requires a pulse longer than two cycles of the count clock selected by prescaler
mode register 01 (PRM01).
p. 146
Timer operation must be stopped before setting other than TOC004.
p. 147
If LVS00 and LVR00 are read, 0 is read.
p. 147
OSPT00 is automatically cleared after data is set, so 0 is read.
p. 147
Soft
Do not set OSPT00 to 1 other than in one-shot pulse output mode.
p. 147
Hard
A write interval of two cycles or more of the count clock selected by prescaler
mode register 00 (PRM00) is required to write to OSPT00 successively.
p. 147
Do not set LVS00 to 1 before TOE00, and do not set LVS00 and TOE00 to 1
simultaneously.
p. 147
TOC00: 16-bit
timer output
control register
00
Perform <1> and <2> below in the following order, not at the same time.
<1> Set TOC001, TOC004, TOE00, OSPE00: Timer output operation setting
<2> Set LVS00, LVR00: Timer output F/F setting
p. 147
Timer operation must be stopped before setting other than TOC014.
p. 148
If LVS01 and LVR01 are read, 0 is read.
p. 148
OSPT01 is automatically cleared after data is set, so 0 is read.
p. 148
Soft
Do not set OSPT01 to 1 other than in one-shot pulse output mode.
p. 148
Hard
A write interval of two cycles or more of the count clock selected by prescaler
mode register 01 (PRM01) is required to write to OSPT01 successively.
p. 148
Do not set LVS01 to 1 before TOE01, and do not set LVS01 and TOE01 to 1
simultaneously.
p. 148
Soft
TOC01: 16-bit
timer output
control register
01
Perform <1> and <2> below in the following order, not at the same time.
<1> Set TOC011, TOC014, TOE01, OSPE01: Timer output operation setting
<2> Set LVS01, LVR01: Timer output F/F setting
p. 148
Hard
When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the
clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the
count clock is the Ring-OSC clock, the operation of 16-bit timer/event counter 00
is not guaranteed. When an external clock is used and when the Ring-OSC clock
is selected and supplied to the CPU, the operation of 16-bit timer/event counter
00 is not guaranteed, either, because the Ring-OSC clock is supplied as the
sampling clock to eliminate noise.
p. 150
Always set data to PRM00 after stopping the timer operation.
p. 150
Chapter 6
Soft
16-bit
timer/
event
counters
00, 01
(TM00,
TM01)
PRM00:
Prescaler mode
register 00
If the valid edge of the TI000 pin is to be set for the count clock, do not set the
clear & start mode using the valid edge of the TI000 pin and the capture trigger.
p. 150
