CHAPTER 10 WATCHDOG TIMER
User’s Manual U16899EJ2V0UD
241
(4) When CPU clock and watchdog timer operation clock are the Ring-OSC clocks (f
R
) during STOP
instruction execution
When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is
released, counting is started again using the operation clock before the operation was stopped. At this time, the
counter is not cleared to 0 but holds its value.
Figure 10-7. Operation in STOP Mode (CPU Clock and WDT Operation Clock: Ring-OSC Clock)
Watchdog timer
Operating
f
R
f
XP
CPU operation
17 clocks
Normal operation
(Ring-OSC clock)
Clock supply stopped
Normal operation (Ring-OSC clock)
Oscillation
stopped
STOP
Oscillation stabilization time
(set by OSTS register)
Operating Operation stopped
10.4.4 Watchdog timer operation in HALT mode (when “Ring-OSC can be stopped by software” is selected by
option byte)
The watchdog timer stops counting during HALT instruction execution regardless of whether the CPU clock is the
high-speed system clock (f
XP
), Ring-OSC clock (f
R
), or subsystem clock (f
XT
), or whether the operation clock of the
watchdog timer is the high-speed system clock (f
XP
) or Ring-OSC clock (f
R
). After HALT mode is released, counting is
started again using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0
but holds its value.
Figure 10-8. Operation in HALT Mode
Watchdog timer
Operating
f
R
f
XP
CPU operation
Normal operation
Operating
HALT
Operation stopped
f
XT
Normal operation
