APPENDIX D LIST OF CAUTIONS
User’s Manual U16899EJ2V0UD
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(2/24)
Chapter
Cl
assi
fi
cati
on
Function Details
of
Function
Cautions Page
−
PCC:
Processor clock
control register
Be sure to clear bit 3 to 0.
p. 112
Soft
Ring-OSC RCM: Ring-
OSC mode
register
Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 1 before
setting RSTOP.
p. 113
Main clock
When Ring-OSC clock is selected as the clock to be supplied to the CPU, the
divided clock of the Ring-OSC oscillator output (f
X
) is supplied to the peripheral
hardware (f
X
= 240 kHz (TYP.)).
Operation of the peripheral hardware with Ring-OSC clock cannot be guaranteed.
Therefore, when Ring-OSC clock is selected as the clock supplied to the CPU, do
not use peripheral hardware. In addition, stop the peripheral hardware before
switching the clock supplied to the CPU from the high-speed system clock to the
Ring-OSC clock. Note, however, that the following peripheral hardware can be
used when the CPU operates on the Ring-OSC clock.
•
Watchdog timer
•
Clock monitor
•
8-bit timer H1 when f
R
/2
7
is selected as count clock
•
Peripheral hardware selecting external clock as the clock source
(Except when external count clock of TM0n (n = 0, 1) is selected (TI00n valid
edge))
p. 114
Hard
Subsystem
clock
MCM: Main
clock mode
register
Set MCS = 1 and MCM0 = 1 before switching subsystem clock operation to high-
speed system clock operation (bit 4 (CSS) of the processor clock control register
(PCC) is changed from 1 to 0).
p. 114
Main clock
Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 0 before
setting MSTOP.
p. 115
Subsystem
clock
MOC: Main
OSC control
register
To stop high-speed system clock oscillation when the CPU is operating on the
subsystem clock, set bit 7 (MCC) of the processor clock control register (PCC) to
1 (setting by MSTOP is not possible).
p. 115
After the above time has elapsed, the bits are set to 1 in order from MOST11 and
remain 1.
p. 116
Soft
If the STOP mode is entered and then released while the Ring-OSC clock is being
used as the CPU clock, set the oscillation stabilization time as follows.
•
Desired OSTC oscillation stabilization time
≤
Oscillation stabilization time set by
OSTS
The oscillation stabilization time counter counts up to the oscillation stabilization
time set by OSTS. Note, therefore, that only the status up to the oscillation
stabilization time set by OSTS is set to OSTC after STOP mode is released.
p. 116
Chapter 5
Hard
Main clock OSTC:
Oscillation
stabilization
time counter
status register
The wait time when STOP mode is released does not include the time after STOP
mode release until clock oscillation starts (“a” below) regardless of whether STOP
mode is released by RESET input or interrupt generation.
p. 116
