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NEC MuPD78F0132H, User Manual

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CHAPTER  15   SERIAL  INTERFACES  CSI10  AND  CSI11 

User’s Manual  U16899EJ2V0UD 

340 

Figure 15-9.  Timing in 3-Wire Serial I/O Mode (1/2)  

 

(1)  Transmission/reception timing (Type 1;  TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 0, SSE11 = 1

Note

) 

 

AAH

ABH

56H

ADH

5AH

B5H

6AH

D5H

55H (communication data)

55H is written to SOTB1n.

SCK1n

SOTB1n

SIO1n

CSOT1n

CSIIF1n

SO1n

SI1n (receive AAH)

Read/write trigger

INTCSI1n

SSI11

Note

 

 

Note  The SSE11 flag and SSI11 pin are available only for serial interface CSI11, and are used in the slave 

mode. 

 

Remark  n = 0: 

µ

PD78F0132H 

 

n = 0, 1: 

µ

PD78F0133H, 78F0134H, 78F0136H, 78F0138H, 78F0138HD 

 

Summary of Contents for MuPD78F0132H

Page 1: ...U16899EJ2V0UD00 2nd edition Date Published April 2005 N CP K Printed in Japan 2003 µPD78F0132H µPD78F0133H µPD78F0134H µPD78F0136H µPD78F0138H µPD78F0138HD 78K0 KE1 8 Bit Single Chip Microcontrollers User s Manual ...

Page 2: ...User s Manual U16899EJ2V0UD 2 MEMO ...

Page 3: ... including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON d...

Page 4: ...NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to p...

Page 5: ...anch Seoul Korea Tel 02 558 3737 NEC Electronics Shanghai Ltd Shanghai P R China Tel 021 5888 5400 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 NEC Electronics Singapore Pte Ltd Novena Square Singapore Tel 6253 8311 J04 1 NEC Electronics Europe GmbH Duesseldorf Germany Tel 0211 65030 Sucursal en España Madrid Spain Tel 091 504 27 87 Vélizy Villacoublay France Tel 01 30 67 58 00 Succur...

Page 6: ... block functions Interrupts Other on chip peripheral functions Electrical specifications CPU functions Instruction set Explanation of each instruction How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering logic circuits and microcontrollers To gain a general understanding of functions Read this manual in the order of the CONTENTS The...

Page 7: ... Minimum instruction execution time 0 125 µs at 16 MHz operation 0 166 µs at 12 MHz operation Related Documents The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such Documents Related to Devices Document Name Document No 78K0 KE1 User s Manual This manual 78K0 KE1 User s Manual U16228E 78K 0 Series Instructions User...

Page 8: ...cument No SEMICONDUCTOR SELECTION GUIDE Products and Packages X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892E Note See the Semiconductor Device Mount Manual website http www necel com pkg en m...

Page 9: ... P43 port 4 38 2 2 6 P50 to P53 port 5 38 2 2 7 P60 to P63 port 6 39 2 2 8 P70 to P77 port 7 39 2 2 9 P120 port 12 39 2 2 10 P130 port 13 39 2 2 11 P140 and P141 port 14 39 2 2 12 AVREF 40 2 2 13 AVSS 40 2 2 14 RESET 40 2 2 15 X1 and X2 40 2 2 16 XT1 and XT2 40 2 2 17 VDD and EVDD 40 2 2 18 VSS and EVSS 40 2 2 19 FLMD0 and FLMD1 40 2 3 Pin I O Circuits and Recommended Connection of Unused Pins 41 ...

Page 10: ...2 Port 1 89 4 2 3 Port 2 94 4 2 4 Port 3 95 4 2 5 Port 4 97 4 2 6 Port 5 98 4 2 7 Port 6 99 4 2 8 Port 7 100 4 2 9 Port 12 101 4 2 10 Port 13 102 4 2 11 Port 14 103 4 3 Registers Controlling Port Function 104 4 4 Port Function Operations 108 4 4 1 Writing to I O port 108 4 4 2 Reading from I O port 108 4 4 3 Operations on I O port 108 CHAPTER 5 CLOCK GENERATOR 109 5 1 Functions of Clock Generator ...

Page 11: ...ons for 16 Bit Timer Event Counters 00 and 01 177 CHAPTER 7 8 BIT TIMER EVENT COUNTERS 50 AND 51 180 7 1 Functions of 8 Bit Timer Event Counters 50 and 51 180 7 2 Configuration of 8 Bit Timer Event Counters 50 and 51 182 7 3 Registers Controlling 8 Bit Timer Event Counters 50 and 51 184 7 4 Operations of 8 Bit Timer Event Counters 50 and 51 189 7 4 1 Operation as interval timer 189 7 4 2 Operation...

Page 12: ...er 243 11 4 Clock Output Buzzer Output Controller Operations 245 11 4 1 Clock output operation 245 11 4 2 Operation as buzzer output 245 CHAPTER 12 A D CONVERTER 246 12 1 Functions of A D Converter 246 12 2 Configuration of A D Converter 247 12 3 Registers Used in A D Converter 249 12 4 A D Converter Operations 254 12 4 1 Basic operations of A D converter 254 12 4 2 Input voltage and conversion re...

Page 13: ...on 351 16 4 2 Division operation 353 CHAPTER 17 INTERRUPT FUNCTIONS 355 17 1 Interrupt Function Types 355 17 2 Interrupt Sources and Configuration 355 17 3 Registers Controlling Interrupt Functions 359 17 4 Interrupt Servicing Operations 367 17 4 1 Maskable interrupt acknowledgement 367 17 4 2 Software interrupt request acknowledgement 369 17 4 3 Multiple interrupt servicing 370 17 4 4 Interrupt r...

Page 14: ...OM Correction 419 25 2 Configuration of ROM Correction 419 25 3 Register Controlling ROM Correction 421 25 4 ROM Correction Usage Example 422 25 5 ROM Correction Application 423 25 6 Program Execution Flow 426 25 7 Cautions for ROM Correction 428 CHAPTER 26 FLASH MEMORY 429 26 1 Internal Memory Size Switching Register 430 26 2 Internal Expansion RAM Size Switching Register 431 26 3 Writing with Fl...

Page 15: ...NDED SOLDERING CONDITIONS 494 CHAPTER 32 CAUTIONS FOR WAIT 495 32 1 Cautions for Wait 495 32 2 Peripheral Hardware That Generates Wait 496 32 3 Example of Wait Occurrence 497 APPENDIX A DEVELOPMENT TOOLS 498 A 1 Software Package 501 A 2 Language Processing Software 501 A 3 Control Software 502 A 4 Flash Memory Writing Tools 502 A 5 Debugging Tools Hardware 503 A 5 1 When using in circuit emulator ...

Page 16: ...0138HD only On chip power on clear POC circuit and low voltage detector LVI Short startup is possible via the CPU default start using the on chip Ring OSC On chip clock monitor function using on chip Ring OSC On chip watchdog timer operable with Ring OSC clock On chip multiplier divider On chip key interrupt function On chip clock output buzzer output controller I O ports 51 N ch open drain 4 Time...

Page 17: ...icals power windows keyless entry reception etc Sub microcontrollers for control Home audio car audio AV equipment PC peripheral equipment keyboards etc Household electrical appliances Outdoor air conditioner units Microwave ovens electric rice cookers Industrial equipment Pumps Vending machines FA Factory Automation ...

Page 18: ...4 pin plastic TQFP 12 12 µPD78F0136HGB 8EU 64 pin plastic LQFP 10 10 µPD78F0136HGC 8BS 64 pin plastic LQFP 14 14 µPD78F0136HGK 9ET 64 pin plastic TQFP 12 12 µPD78F0138HGB 8EU 64 pin plastic LQFP 10 10 µPD78F0138HGC 8BS 64 pin plastic LQFP 14 14 µPD78F0138HGK 9ET 64 pin plastic TQFP 12 12 µPD78F0138HF1 BA2 Note 1 64 pin plastic FBGA 6 6 µPD78F0138HDGB 8EU Note 2 64 pin plastic LQFP 10 10 µPD78F0138...

Page 19: ...Z INTP7 P17 TI50 TO50 FLMD1 P16 TOH1 INTP5 P15 TOH0 P14 RxD6 P13 TxD6 P12 SO10 P11 SI10 RxD0 P10 SCK10 TxD0 P60 P61 P62 P63 EV SS P40 P41 P42 P43 P50 P51 P52 P53 P00 TI000 P01 TI010 TO00 P02 SO11Note P03 SI11Note P04 SCK11Note P05 SSI11Note TI001Note P06 TI011Note TO01Note EVDD AVREF AVSS FLMD0 VDD NC VSS X1 X2 RESET XT1 XT2 P130 P120 INTP0 P33 TI51 TO51 INTP4 P32 INTP3 P31 INTP2 64 63 62 61 60 59...

Page 20: ...CK10 TxD0 G3 P04 SCK11 A4 X2 C4 P130 E4 P62 G4 P01 TI010 TO00 A5 VSS C5 RESET E5 P52 G5 P50 A6 FLMD0 C6 P23 ANI3 E6 P70 KR0 G6 P42 A7 AVSS C7 P22 ANI2 E7 P71 KR1 G7 P76 KR6 A8 AVREF C8 P24 ANI4 E8 P73 KR3 G8 P77 KR7 B1 P140 PCL INTP6 D1 P14 RxD6 F1 P61 H1 EVSS B2 P33 TI51 TO51 INTP4 D2 P13 TxD6 F2 P60 H2 EVDD B3 P120 INTP0 D3 P15 TOH0 F3 P02 SO11 H3 P03 SI11 B4 XT1 D4 P16 TOH1 INTP5 F4 P53 H4 P06 ...

Page 21: ...P70 to P77 Port 7 P120 Port 12 P130 Port 13 P140 P141 Port 14 PCL Programmable clock output RESET Reset RxD0 RxD6 Receive data SCK10 SCK11Note Serial clock input output SI10 SI11Note Serial data input SO10 SO11 Note Serial data output SSI11Note Serial interface chip select input TI000 TI010 TI001Note TI011 Note TI50 TI51 Timer input TO00 TO01Note TO50 TO51 TOH0 TOH1 Timer output TxD0 TxD6 Transmit...

Page 22: ...er supply flash memory 24 KB RAM 1 KB Single power supply flash memory 16 KB RAM 512 B 78K0 KD1 PD78F0123H PD78F0124H HDNote PD78F0122H Two power supply flash memory 32 KB RAM 1 KB PD78F0148 Mask ROM 60 KB RAM 2 KB PD780148 Mask ROM 48 KB RAM 2 KB PD780146 Mask ROM 32 KB RAM 1 KB PD780144 Mask ROM 24 KB RAM 1 KB PD780143 80 pin TQFP QFP 12 12 mm 0 5 mm pitch 14 14 mm 0 65 mm pitch Single power sup...

Page 23: ...tch 1 ch Timer WDT 1 ch 3 wire CSI Note 3 1 ch 2 ch 1 ch 2 ch Automatic transmit receive 3 wire CSI 1 ch UART Note 3 1 ch Serial interface UART supporting LIN bus 1 ch 10 bit A D converter 4 ch 8 ch External 6 7 8 9 9 Interrupt Internal 11 12 15 16 19 17 20 Key return input 4 ch 8 ch RESET pin Provided POC 2 85 V 0 15 V 3 5 V 0 20 V selectable by mask option LVI 2 85 V 3 1 V 3 3 V 0 15 V 3 5 V 3 7...

Page 24: ...H 2 ch For watch 1 ch Timer WDT 1 ch 3 wire CSI Note 2 1 ch 2 ch Automatic transmit receive 3 wire CSI 1 ch UART Note 2 1 ch Serial interface UART supporting LIN bus 1 ch 10 bit A D converter 4 ch 8 ch External 6 7 8 9 9 Interrupts Internal 11 12 15 16 19 20 Key return input 4 ch 8 ch RESET pin Provided POC 2 1 V 0 1 V detection voltage is fixed LVI 2 35 V 2 6 V 2 85 V 3 1 V 3 3 V 0 15 V 3 5 V 3 7...

Page 25: ...8 Single power supply flash memory 256 KB RAM 12 KB PD703308Y PD703308 Mask ROM 256 KB RAM 12 KB PD703214Y PD703214 Mask ROM 128 KB RAM 6 KB PD703213Y PD703213 Mask ROM 96 KB RAM 4 KB PD70F3214HY PD70F3214H Single power supply flash memory 128 KB RAM 6 KB PD70F3311Y PD70F3311 Single power supply flash memory 128 KB RAM 6 KB PD70F3214Y PD70F3214 Two power supply flash memory 128 KB RAM 6 KB PD70321...

Page 26: ...h 1 ch For watch 1 ch 1 ch 1 ch 1 ch WDT1 1 ch 1 ch 1 ch 1 ch Timer WDT2 1 ch 1 ch 1 ch 1 ch RTO 6 bits 1 ch 6 bits 1 ch 6 bits 1 ch 6 bits 2 ch CSI 2 ch 2 ch 2 ch 3 ch Automatic transmit receive 3 wire CSI 1 ch 2 ch 2 ch UART 2 ch 2 ch 2 ch 3 ch UART supporting LIN bus Serial interface I 2 C Note 1 ch 1 ch 1 ch 2 ch Address space 128 KB 3 MB 15 MB Address bus 16 bits 22 bits 24 bits External bus ...

Page 27: ...DT2 1 ch 1 ch 1 ch 1 ch RTO 6 bits 1 ch 6 bits 1 ch 6 bits 1 ch 6 bits 2 ch CSI 2 ch 2 ch 2 ch 3 ch Automatic transmit receive 3 wire CSI 1 ch 2 ch 2 ch UART 1 ch 1 ch 1 ch 2 ch UART supporting LIN bus 1 ch 1 ch 1 ch 1 ch Serial interface I 2 C Note 1 ch 1 ch 1 ch 2 ch Address space 128 KB 3 MB 15 MB Address bus 16 bits 22 bits 24 bits External bus Mode Multiplexed mode only Multiplexed separate m...

Page 28: ...SS INTP1 P30 to INTP4 P33 4 INTP0 P120 8 System control RESET X1 X2 Clock monitor Power on clear low voltage indicator Reset control Port 6 P60 to P63 4 Port 7 P70 to P77 Port 12 P120 Port 13 P130 8 P40 to P43 4 P50 to P53 4 Port 14 P140 P141 2 Ring OSC XT1 XT2 16 bit timer Note 1 event counter 01 TO01Note 1 TI011Note 1 P06 TI001Note 1 P05 TI51 TO51 P33 8 bit timer event counter 51 Watch timer Ser...

Page 29: ...cution time 122 µs subsystem clock when operating at fXT 32 768 kHz Instruction set 16 bit operation Multiply divide 8 bits 8 bits 16 bits 8 bits Bit manipulate set reset test and Boolean operation BCD adjust etc I O ports Total 51 CMOS I O 38 CMOS input 8 CMOS output 1 N ch open drain I O 4 Timers 16 bit timer event counter 2 channels 1 channel only in the µPD78F0132H 8 bit timer event counter 2 ...

Page 30: ...eset using RESET pin Internal reset by watchdog timer Internal reset by clock monitor Internal reset by power on clear Internal reset by low voltage detector ROM correction Provided On chip debug function Provided Supply voltage VDD 2 5 to 5 5 V with Ring OSC clock or subsystem clock VDD 2 0 to 5 5 V Note 2 Operating ambient temperature TA 40 to 85 C Package 64 pin plastic LQFP 10 10 64 pin plasti...

Page 31: ...n mode Watchdog timer 1 channel Timer output 1 output 1 output 1 output 1 output 1 output 1 output PPG output 1 output 1 output PWM output 1 output 1 output 1 output 1 output Pulse width measurement 2 inputs 2 inputs Square wave output 1 output 1 output 1 output 1 output 1 output 1 output Function Interrupt source 2 2 1 1 1 1 1 Notes 1 16 bit timer event counter 01 is available only in the µPD78F0...

Page 32: ... output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a software setting Input TI011 Note TO01 Note P10 SCK10 TxD0 P11 SI10 RxD0 P12 SO10 P13 TxD6 P14 RxD6 P15 TOH0 P16 TOH1 INTP5 P17 I O Port 1 8 bit I O port Input output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a software setting Input TI50 TO50 FLMD1 P20 to P...

Page 33: ...tting Input P60 to P63 I O Port 6 4 bit I O port N ch open drain Input output can be specified in 1 bit units Input P70 to P77 I O Port 7 8 bit I O port Input output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a software setting Input KR0 to KR7 P120 I O Port 12 1 bit I O port Use of an on chip pull up resistor can be specified by a software setting Input...

Page 34: ...P00 TI001 Note External count clock input to 16 bit timer event counter 01 Capture trigger input to capture registers CR001 CR011 of 16 bit timer event counter 01 P05 SSI11 Note TI010 Capture trigger input to capture register CR000 of 16 bit timer event counter 00 P01 TO00 TI011 Note Input Capture trigger input to capture register CR001 of 16 bit timer event counter 01 Input P06 TO01 Note TO00 16 ...

Page 35: ... as EVSS or VSS KR0 to KR7 Input Key interrupt input Input P70 to P77 RESET Input System reset input X1 Input X2 Connecting resonator for high speed system clock XT1 Input XT2 Connecting resonator for subsystem clock VDD Positive power supply except for ports EVDD Positive power supply for ports VSS Ground potential except for ports EVSS Ground potential for ports FLMD0 FLMD1 Flash memory programm...

Page 36: ...ct input a TI000 TI001Note These are the pins for inputting an external count clock to 16 bit timer event counters 00 and 01 and are also for inputting a capture trigger signal to the capture registers CR000 CR010 or CR001 CR011 of 16 bit timer event counters 00 and 01 b TI010 TI011Note These are the pins for inputting a capture trigger signal to the capture register CR000 or CR001 of 16 bit timer...

Page 37: ... interrupt request input serial interface data I O clock I O timer I O and flash memory programming mode setting a SI10 This is a serial interface serial data input pin b SO10 This is a serial interface serial data output pin c SCK10 This is a serial interface serial clock I O pin d RxD0 RxD6 These are the serial data input pins of the asynchronous serial interface e TxD0 TxD6 These are the serial...

Page 38: ...P30 to P33 function as external interrupt request input pins and timer I O pins a INTP1 to INTP4 These are the external interrupt request input pins for which the valid edge rising edge falling edge or both rising and falling edges can be specified b TI51 This is an external count clock input pin to 8 bit timer event counter 51 c TO51 This is a timer output pin Caution In the µPD78F0138HD be sure ...

Page 39: ...0 can be set to input or output using port mode register 12 PM12 Use of an on chip pull up resistor can be specified by pull up resistor option register 12 PU12 2 Control mode P120 functions as an external interrupt request input pin INTP0 for which the valid edge rising edge falling edge or both rising and falling edges can be specified 2 2 10 P130 port 13 P130 functions as a 1 bit output only po...

Page 40: ...inverse signal to the X2 pin Remark The X1 and X2 pins of the µPD78F0138HD can be used as on chip debug mode setting pins when the on chip debug function is used For details refer to CHAPTER 27 ON CHIP DEBUG FUNCTION µPD78F0138HD ONLY 2 2 16 XT1 and XT2 These are the pins for connecting a resonator for subsystem clock When supplying an external clock input a signal to the XT1 pin and input the inv...

Page 41: ...eave open P20 ANI0 to P27 ANI7 9 C Input Connect to EVDD or EVSS P30 INTP1 P31 INTP2 except µPD78F0138HD Input Independently connect to EVDD or EVSS via a resistor Output Leave open P31 INTP2 µPD78F0138HD Connect to EVSS via a resistor P32 INTP3 P33 TI51 TO51 INTP4 8 A P40 to P43 P50 to P53 5 A Input Independently connect to EVDD or EVSS via a resistor Output Leave open P60 P61 13 R P62 P63 13 W I...

Page 42: ...fter reset mode is released 2 Connect port 2 directly to EVDD when it is used as a digital port Pin Name I O Circuit Type I O Recommended Connection of Unused Pins RESET 2 Connect to EVDD or VDD XT1 Input Connect directly to EVSS or VSS Note 1 XT2 16 Leave open AVREF Connect directly to EVDD or VDD Note 2 AVSS Connect directly to EVSS or VSS FLMD0 Connect to EVSS or VSS ...

Page 43: ...C Schmitt triggered input with hysteresis characteristics IN Pullup enable Data Output disable EVDD P ch VDD P ch IN OUT N ch EVDD P ch N ch Data OUT IN Comparator VREF threshold voltage AVSS P ch N ch Input enable Pullup enable Data Output disable Input enable EVDD P ch VDD P ch IN OUT N ch Data Output disable IN OUT N ch Type 13 R ...

Page 44: ...ER 2 PIN FUNCTIONS User s Manual U16899EJ2V0UD 44 Figure 2 1 Pin I O Circuit List 2 2 Type 13 W Type 16 Data Output disable IN OUT N ch Input enable Middle voltage input buffer P ch Feedback cut off XT1 XT2 ...

Page 45: ...ed IMS CFH IXS 0CH Therefore set the value corresponding to each product as indicated below In addition set the following values to the IMS and the IXS when using the 78K0 KE1 to evaluate the program of a mask ROM version of the 78K0 KE1 Table 3 1 Set Values of Internal Memory Size Switching Register IMS and Internal Expansion RAM Size Switching Register IXS Flash Memory Version 78K0 KE1 Target Ma...

Page 46: ...ce Data memory space Vector table area H CALLT table area Program area CALLF entry area Program area 0 0 0 0 H F 3 0 0 H 0 4 0 0 H F 7 0 0 H 0 8 0 0 H F F 7 0 H 0 0 8 0 H F F F 0 H 0 0 0 1 H F F F 3 H 0 0 0 0 H F F F 3 H 0 0 0 4 H F F C F H 0 0 D F H F D E F H 0 E E F H F F E F H 0 0 F F H F F F F H 1 8 0 0 Option byte area Caution When replacing the µPD78F0132H with the µPD78F0138HD note that the...

Page 47: ...ce Data memory space Vector table area H CALLT table area Program area CALLF entry area Program area 0 0 0 0 H F 3 0 0 H 0 4 0 0 H F 7 0 0 H 0 8 0 0 H F F 7 0 H 0 0 8 0 H F F F 0 H 0 0 0 1 H F F F 5 H 0 0 0 0 H F F F 5 H 0 0 0 6 H F F A F H 0 0 B F H F D E F H 0 E E F H F F E F H 0 0 F F H F F F F Option byte area H 1 8 0 0 Caution When replacing the µPD78F0133H with the µPD78F0138HD note that the...

Page 48: ...ce Data memory space Vector table area H CALLT table area Program area CALLF entry area Program area 0 0 0 0 H F 3 0 0 H 0 4 0 0 H F 7 0 0 H 0 8 0 0 H F F 7 0 H 0 0 8 0 H F F F 0 H 0 0 0 1 H F F F 7 H 0 0 0 0 H F F F 7 H 0 0 0 8 H F F A F H 0 0 B F H F D E F H 0 E E F H F F E F H 0 0 F F H F F F F H 1 8 0 0 Option byte area Caution When replacing the µPD78F0134H with the µPD78F0138HD note that the...

Page 49: ...its Internal high speed RAM 1024 8 bits General purpose registers 32 8 bits Reserved Flash memory 49152 8 bits Program memory space Data memory space Vector table area CALLT table area Program area CALLF entry area Program area Reserved Internal expansion RAM 1024 8 bits Option byte area 0081H RAM space in which instruction can be fetched Caution When replacing the µPD78F0136H with the µPD78F0138H...

Page 50: ...its Internal high speed RAM 1024 8 bits General purpose registers 32 8 bits Reserved Flash memory 61440 8 bits Program memory space Data memory space Vector table area CALLT table area Program area CALLF entry area Program area Reserved Internal expansion RAM 1024 8 bits Option byte area 0081H RAM space in which instruction can be fetched Caution When replacing the µPD78F0138H with the µPD78F0138H...

Page 51: ...mory space Data memory space Vector table area CALLT table area CALLF entry area Program area Reserved Internal expansion RAM 1024 8 bits Note 2 RAM space in which instruction can be fetched Note 1 FB00H FAFFH 0080H 007FH Program area Option byte area 0081H Note 2 Reserved for option byte 0084H 0083H 0190H 018FH Notes 1 During on chip debugging 9 bytes of this area are used as the user data backup...

Page 52: ...eserved as a vector table area The program start addresses for branch upon reset signal input or generation of each interrupt request are stored in the vector table area Of the 16 bit address the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses Table 3 3 Vector Table Vector Table Address Interrupt Source Vector Table Address Interrupt Source 0020H INTTM00...

Page 53: ...F0132H 512 8 bits FD00H to FEFFH µPD78F0133H µPD78F0134H µPD78F0136H µPD78F0138H 78F0138HD 1024 8 bits FB00H to FEFFH The 32 byte area FEE0H to FEFFH is assigned to four general purpose register banks consisting of eight 8 bit registers per one bank This area cannot be used as a program area in which instructions are written and executed The internal high speed RAM can also be used as a stack memo...

Page 54: ...sed on operability and other considerations For areas containing data memory in particular special addressing methods designed for the functions of special function registers SFR and general purpose registers are available for use Figures 3 7 to 3 12 show correspondence between data memory and addressing For details of each addressing mode refer to 3 4 Operand Address Addressing Figure 3 7 Corresp...

Page 55: ...ct addressing SFR addressing Internal high speed RAM 1024 8 bits General purpose registers 32 8 bits Reserved Flash memory 24576 8 bits Register addressing Direct addressing Register indirect addressing Based addressing Based indexed addressing H 0 0 0 0 H F F F 5 H 0 0 0 6 H F F A F H 0 0 B F H F D E F H 0 E E F H F F E F H 0 0 F F H F F F F H F 1 E F H 0 2 E F H F 1 F F H 0 2 F F ...

Page 56: ...ct addressing SFR addressing Internal high speed RAM 1024 8 bits General purpose registers 32 8 bits Reserved Flash memory 32768 8 bits Register addressing Direct addressing Register indirect addressing Based addressing Based indexed addressing H 0 0 0 0 H F F F 7 H 0 0 0 8 H F F A F H 0 0 B F H F D E F H 0 E E F H F F E F H 0 0 F F H F F F F H F 1 E F H 0 2 E F H F 1 F F H 0 2 F F ...

Page 57: ...FH C000H BFFFH F800H F7FFH F400H F3FFH FB00H FAFFH Special function registers SFR 256 8 bits Short direct addressing SFR addressing Internal high speed RAM 1024 8 bits General purpose registers 32 8 bits Reserved Flash memory 49152 8 bits Register addressing Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved Internal expansion RAM 1024 8 bits ...

Page 58: ...FH F000H EFFFH F800H F7FFH F400H F3FFH FB00H FAFFH Special function registers SFR 256 8 bits Short direct addressing SFR addressing Internal high speed RAM 1024 8 bits General purpose registers 32 8 bits Reserved Flash memory 61440 8 bits Register addressing Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved Internal expansion RAM 1024 8 bits ...

Page 59: ... 1024 8 bits General purpose registers 32 8 bits Reserved Flash memory 61440 8 bits Register addressing Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved Internal expansion RAM 1024 8 bits FB00H FAFFH Note 1 Note 2 Notes 1 During on chip debugging 9 bytes of this area are used as the user data backup area for communication 2 During on chip debugging ...

Page 60: ...C6 PC5 PC4 PC3 PC2 PC1 PC0 2 Program status word PSW The program status word is an 8 bit register consisting of various flags set reset by instruction execution Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are restored upon execution of the RETB RETI and POP PSW instructions RESET input sets the PSW to 02H Figure 3 1...

Page 61: ...3 3 Priority specification flag registers PR0L PR0H PR1L PR1H can not be acknowledged Actual request acknowledgement is controlled by the interrupt enable flag IE f Carry flag CY This flag stores overflow and underflow upon add subtract instruction execution It stores the shift out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution...

Page 62: ...struction when SP FEE0H Register pair lower FEE0H SP SP FEE0H FEDFH FEDEH Register pair higher FEDEH b CALL CALLF CALLT instructions when SP FEE0H PC15 to PC8 FEE0H SP SP FEE0H FEDFH FEDEH PC7 to PC0 FEDEH c Interrupt BRK instructions when SP FEE0H PC15 to PC8 PSW FEDFH FEE0H SP SP FEE0H FEDEH FEDDH PC7 to PC0 FEDDH ...

Page 63: ...a POP rp instruction when SP FEDEH Register pair lower FEE0H SP SP FEE0H FEDFH FEDEH Register pair higher FEDEH b RET instruction when SP FEDEH PC15 to PC8 FEE0H SP SP FEE0H FEDFH FEDEH PC7 to PC0 FEDEH c RETI RETB instructions when SP FEDDH PC15 to PC8 PSW FEDFH FEE0H SP SP FEE0H FEDEH FEDDH PC7 to PC0 FEDDH ...

Page 64: ... C B E D L H AX BC DE and HL and absolute names R0 to R7 and RP0 to RP3 Register banks to be used for instruction execution are set by the CPU control instruction SEL RBn Because of the 4 register bank configuration an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank Figure 3 18 Configuration of General Purpose Regis...

Page 65: ...tion instruction operand sfr This manipulation can also be specified with an address 16 bit manipulation Describe the symbol reserved by the assembler for the 16 bit manipulation instruction operand sfrp When specifying an address describe an even address Table 3 6 gives a list of the special function registers The meanings of items in the table are as follows Symbol Symbol indicating the address ...

Page 66: ...bit timer capture compare register 000 CR000 R W 0000H FF14H FF15H 16 bit timer capture compare register 010 CR010 R W 0000H FF16H 8 bit timer counter 50 TM50 R 00H FF17H 8 bit timer compare register 50 CR50 R W 00H FF18H 8 bit timer H compare register 00 CMP00 R W 00H FF19H 8 bit timer H compare register 10 CMP10 R W 00H FF1AH 8 bit timer H compare register 01 CMP01 R W 00H FF1BH 8 bit timer H co...

Page 67: ...rrupt falling edge enable register EGN R W 00H FF4AH Serial I O shift register 11 Note 2 SIO11 R 00H FF4CH Transmit buffer register 11 Note 2 SOTB11 R W Undefined FF4FH Input switch control register ISC R W 00H FF50H Asynchronous serial interface operation mode register 6 ASIM6 R W 01H FF53H Asynchronous serial interface reception error status register 6 ASIS6 R 00H FF55H Asynchronous serial inter...

Page 68: ...e 2 CORCN R W 00H FF8CH Timer clock selection register 51 TCL51 R W 00H FF98H Watchdog timer mode register WDTM R W 67H FF99H Watchdog timer enable register WDTE R W 9AH FFA0H Ring OSC mode register RCM R W 00H FFA1H Main clock mode register MCM R W 00H FFA2H Main OSC control register MOC R W 00H FFA3H Oscillation stabilization time counter status register OSTC R 00H FFA4H Oscillation stabilizatio...

Page 69: ...g register 1H MK1H R W DFH FFE8H Priority specification flag register 0L PR0 PR0L R W FFH FFE9H Priority specification flag register 0H PR0H R W FFH FFEAH Priority specification flag register 1L PR1 PR1L R W FFH FFEBH Priority specification flag register 1H PR1H R W FFH FFF0H Internal memory size switching register Note 2 IMS R W CFH FFF4H Internal expansion RAM size switching register Note 2 IXS ...

Page 70: ...dressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes a sign bit In other words relative addressing consists of relative branching from th...

Page 71: ... CALL addr16 or BR addr16 or CALLF addr11 instruction is executed CALL addr16 and BR addr16 instructions can be branched to the entire memory space The CALLF addr11 instruction is branched to the 0800H to 0FFFH area Illustration In the case of CALL addr16 and BR addr16 instructions 15 0 PC 8 7 7 0 CALL or BR Low Addr High Addr In the case of CALLF addr11 instruction 15 0 PC 8 7 7 0 fa10 8 11 10 0 ...

Page 72: ...d This instruction references the address stored in the memory table from 40H to 7FH and allows branching to the entire memory space Illustration 15 1 15 0 PC 7 0 Low Addr High Addr Memory Table Effective address 1 Effective address 0 1 0 0 0 0 0 0 0 0 8 7 8 7 6 5 0 0 1 1 1 7 6 5 1 0 ta4 0 Operation code 3 3 4 Register addressing Function Register pair AX contents to be specified with an instructi...

Page 73: ... Register to Be Specified by Implied Addressing MULU A register for multiplicand and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA ADJBS A register for storage of numeric values that become decimal correction targets ROR4 ROL4 A register for storage of digit data that undergoes digit rotation Operand format Because implied addressing can be automatically...

Page 74: ...ing operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format Identifier Description r X A C B E D L H rp AX BC DE HL r and rp can be described by absolute names R0 to R7 and RP0 to RP3 as well as function names X A C B E D L H AX BC DE and HL Description example MOV A C when selecting C register as r Ope...

Page 75: ...ith immediate data in an instruction word becoming an operand address Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A 0FE00H when setting addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH Illustration Memory 0 7 addr16 lower addr16 upper OP code ...

Page 76: ...nter are mapped in this area allowing SFRs to be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it is at 00H to 1FH bit 8 is set to 1 Refer to the Illustration shown below Operand format Identifier Description saddr Immediate data that indicate label or FE20H to FF1FH saddrp Immediate data that indicate ...

Page 77: ... to FFCFH and FFE0H to FFFFH However the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing Operand format Identifier Description sfr Special function register name sfrp 16 bit manipulatable special function register name even address only Description example MOV PM0 A when selecting PM0 FF20H as sfr Operation code 1 1 1 1 0 1 1 0 OP code 0 0 1 0 0 0 0 0 20H sfr offset Illu...

Page 78: ...ag RBS0 and RBS1 serve as an operand address for addressing the memory This addressing can be carried out for all the memory spaces Operand format Identifier Description DE HL Description example MOV A DE when selecting DE as register pair Operation code 1 0 0 0 0 1 0 1 Illustration 16 0 8 D 7 E 0 7 7 0 A DE The contents of the memory addressed are transferred Memory The memory address specified w...

Page 79: ...S1 and the sum is used to address the memory Addition is performed by expanding the offset data as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Identifier Description HL byte Description example MOV A HL 10H when setting byte to 10H Operation code 1 0 1 0 1 1 1 0 0 0 0 1 0 0 0 0 Illustration 16 0 8 H 7...

Page 80: ... RBS0 and RBS1 and the sum is used to address the memory Addition is performed by expanding the B or C register contents as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Identifier Description HL B HL C Description example In the case of MOV A HL B selecting B register Operation code 1 0 1 0 1 0 1 1 Ill...

Page 81: ...omatically employed when the PUSH POP subroutine call and return instructions are executed or the register is saved reset upon generation of an interrupt request With stack addressing only the internal high speed RAM area can be accessed Description example In the case of PUSH DE saving DE register Operation code 1 0 1 1 0 1 0 1 Illustration E FEE0H SP SP FEE0H FEDFH FEDEH D Memory 0 7 FEDEH ...

Page 82: ... than P20 to P27 78K0 KE1 products are provided with the ports shown in Figure 4 1 which enable variety of control operations The functions of each port are shown in Table 4 2 In addition to the function as digital I O ports these ports have several alternate functions For details of the alternate functions refer to CHAPTER 2 PIN FUNCTIONS Figure 4 1 Port Types Port 2 P20 P27 Port 3 P30 P33 Port 5...

Page 83: ... P30 to P32 INTP1 to INTP3 P33 I O Port 3 4 bit I O port Input output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a software setting Input INTP4 TI51 TO51 P40 to P43 I O Port 4 4 bit I O port Input output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a software setting Input P50 to P53 I O Port 5 4 bit I O port Inp...

Page 84: ...Port 14 2 bit I O port Input output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a software setting Input BUZ INTP7 4 2 Port Configuration Ports include the following hardware Table 4 3 Port Configuration Item Configuration Control registers Port mode register PM0 PM1 PM3 to PM7 PM12 PM14 Port register P0 to P7 P12 to P14 Pull up resistor option register P...

Page 85: ...clock I O RESET input sets port 0 to input mode Figures 4 2 to 4 5 show block diagrams of port 0 Caution When P02 SO11Note P03 SI11 Note and P04 SCK11 Note are used as general purpose ports do not write to serial clock selection register 11 CSIC11 Figure 4 2 Block Diagram of P00 P03 and P05 P00 TI000 P03 SI11Note P05 SSI11Note TI001Note WRPU RD WRPORT WRPM PU00 PU03 PU05 Alternate function Output ...

Page 86: ...e TO01Note WRPU RD WRPORT WRPM PU01 PU06 Alternate function Output latch P01 P06 PM01 PM06 Alternate function EVDD P ch Selector Internal bus PU0 PM0 Note Available only in the µPD78F0133H 78F0134H 78F0136H 78F0138H and 78F0138HD PU0 Pull up resistor option register 0 PM0 Port mode register 0 RD Read signal WR Write signal ...

Page 87: ...2 SO11Note WRPU RD WRPORT WRPM PU02 Output latch P02 PM02 Alternate function EVDD P ch Selector Internal bus PU0 PM0 Note Available only in the µPD78F0133H 78F0134H 78F0136H 78F0138H and 78F0138HD PU0 Pull up resistor option register 0 PM0 Port mode register 0 RD Read signal WR Write signal ...

Page 88: ...e WRPU RD WRPORT WRPM PU04 Alternate function Output latch P04 PM04 Alternate function EVDD P ch Selector Internal bus PU0 PM0 Note Available only in the µPD78F0133H 78F0134H 78F0136H 78F0138H and 78F0138HD PU0 Pull up resistor option register 0 PM0 Port mode register 0 RD Read signal WR Write signal ...

Page 89: ...l interrupt request input serial interface data I O clock I O timer I O and flash memory programming mode setting RESET input sets port 1 to input mode Figures 4 6 to 4 10 show block diagrams of port 1 Caution When P10 SCK10 TxD0 P11 SI10 RxD0 and P12 SO10 are used as general purpose ports do not write to serial clock selection register 10 CSIC10 Figure 4 6 Block Diagram of P10 P10 SCK10 TxD0 WRPU...

Page 90: ... Block Diagram of P11 and P14 P11 SI10 RxD0 P14 RxD6 WRPU RD WRPORT WRPM PU11 PU14 Alternate function Output latch P11 P14 PM11 PM14 EVDD P ch Selector Internal bus PU1 PM1 PU1 Pull up resistor option register 1 PM1 Port mode register 1 RD Read signal WR Write signal ...

Page 91: ...4 8 Block Diagram of P12 and P15 P12 SO10 P15 TOH0 WRPU RD WRPORT WRPM PU12 PU15 Output latch P12 P15 PM12 PM15 Alternate function EVDD P ch Selector Internal bus PU1 PM1 PU1 Pull up resistor option register 1 PM1 Port mode register 1 RD Read signal WR Write signal ...

Page 92: ...V0UD 92 Figure 4 9 Block Diagram of P13 P13 TxD6 WRPU RD WRPORT WRPM PU13 Output latch P13 PM13 Alternate function EVDD P ch Internal bus Selector PU1 PM1 PU1 Pull up resistor option register 1 PM1 Port mode register 1 RD Read signal WR Write signal ...

Page 93: ...of P16 and P17 P16 TOH1 INTP5 P17 TI50 TO50 FLMD1 WRPU RD WRPORT WRPM PU16 PU17 Alternate function Output latch P16 P17 PM16 PM17 Alternate function EVDD P ch Selector Internal bus PU1 PM1 PU1 Pull up resistor option register 1 PM1 Port mode register 1 RD Read signal WR Write signal ...

Page 94: ... 4 2 3 Port 2 Port 2 is an 8 bit input only port This port can also be used for A D converter analog input Figure 4 11 shows a block diagram of port 2 Figure 4 11 Block Diagram of P20 to P27 RD A D converter P20 ANI0 to P27 ANI7 Internal bus RD Read signal ...

Page 95: ...o input mode Figures 4 12 and 4 13 show block diagrams of port 3 Caution In the µPD78F0138HD be sure to pull the P31 pin down after reset to prevent malfunction Remark P31 INTP2 and P32 INTP3 of the µPD78F0138HD can be used for on chip debug mode setting when the on chip debug function is used For details refer to CHAPTER 27 ON CHIP DEBUG FUNCTION µPD78F0138HD ONLY Figure 4 12 Block Diagram of P30...

Page 96: ...4 13 Block Diagram of P33 P33 INTP4 TI51 TO51 WRPU RD WRPORT WRPM PU33 Alternate function Output latch P33 PM33 Alternate function EVDD P ch Selector Internal bus PU3 PM3 PU3 Pull up resistor option register 3 PM3 Port mode register 3 RD Read signal WR Write signal ...

Page 97: ...p pull up resistor can be specified in 1 bit units with pull up resistor option register 4 PU4 RESET input sets port 4 to input mode Figure 4 14 shows a block diagram of port 4 Figure 4 14 Block Diagram of P40 to P43 RD P ch WRPU WRPORT WRPM EVDD P40 to P43 PU40 to PU43 Output latch P40 to P43 PM40 to PM43 Selector Internal bus PU4 PM4 PU4 Pull up resistor option register 4 PM4 Port mode register ...

Page 98: ... pull up resistor can be specified in 1 bit units using pull up resistor option register 5 PU5 RESET input sets port 5 to input mode Figure 4 15 shows a block diagram of port 5 Figure 4 15 Block Diagram of P50 to P53 RD P ch WRPU WRPORT WRPM EVDD P50 to P53 PU50 to PU53 Output latch P50 to P53 PM50 to PM53 Selector Internal bus PU5 PM5 PU5 Pull up resistor option register 5 PM5 Port mode register ...

Page 99: ... mode in 1 bit units using port mode register 6 PM6 The P60 to P63 pins are N ch open drain pins RESET input sets port 6 to input mode Figure 4 16 shows a block diagram of port 6 Figure 4 16 Block Diagram of P60 to P63 RD P60 to P63 WRPORT WRPM Output latch P60 to P63 PM60 to PM63 Selector Internal bus PM6 PM6 Port mode register 6 RD Read signal WR Write signal ...

Page 100: ...resistor can be specified in 1 bit units by pull up resistor option register 7 PU7 This port can also be used for key return input RESET input sets port 7 to input mode Figure 4 17 shows a block diagram of port 7 Figure 4 17 Block Diagram of P70 to P77 P70 KR0 to P77 KR7 WRPU RD WRPORT WRPM PU70 to PU77 Alternate function Output latch P70 to P77 PM70 to PM77 EVDD P ch Selector Internal bus PU7 PM7...

Page 101: ... resistor can be specified by pull up resistor option register 12 PU12 This port can also be used for external interrupt request input RESET input sets port 12 to input mode Figure 4 18 shows a block diagram of port 12 Figure 4 18 Block Diagram of P120 P120 INTP0 WRPU RD WRPORT WRPM PU120 Alternate function Output latch P120 PM120 EVDD P ch Selector Internal bus PU12 PM12 PU12 Pull up resistor opt...

Page 102: ... a block diagram of port 13 Figure 4 19 Block Diagram of P130 RD Output latch P130 WRPORT P130 Internal bus RD Read signal WR Write signal Remark When reset is effected P130 outputs a low level If P130 is set to output a high level before reset is effected the output signal of P130 can be dummy output as the CPU reset signal ...

Page 103: ... by pull up resistor option register 14 PU14 This port can also be used for external interrupt request input buzzer output and clock output RESET input sets port 14 to input mode Figure 4 20 shows a block diagram of port 14 Figure 4 20 Block Diagram of P140 and P141 P140 PCL INTP6 P141 BUZ INTP7 WRPU RD WRPORT WRPM PU140 PU141 Alternate function Output latch P140 P141 PM140 PM141 Alternate functio...

Page 104: ...rt mode register and output latch as shown in Table 4 4 Figure 4 21 Format of Port Mode Register 7 1 Symbol PM0 6 PM06 5 PM05 4 PM04 3 PM03 2 PM02 1 PM01 0 PM00 Address FF20H After reset FFH R W R W 7 PM17 PM1 6 PM16 5 PM15 4 PM14 3 PM13 2 PM12 1 PM11 0 PM10 FF21H FFH R W 7 1 PM3 6 1 5 1 4 1 3 PM33 2 PM32 1 PM31 0 PM30 FF23H FFH R W 7 1 PM4 6 1 5 1 4 1 3 PM43 2 PM42 1 PM41 0 PM40 FF24H FFH R W 7 1...

Page 105: ...ut 0 0 Input 1 SCK10 Output 0 1 P10 TxD0 Output 0 1 SI10 Input 1 P11 RxD0 Input 1 P12 SO10 Output 0 0 P13 TxD6 Output 0 1 P14 RxD6 Input 1 P15 TOH0 Output 0 0 TOH1 Output 0 0 P16 INTP5 Input 1 TI50 Input 1 P17 TO50 Output 0 0 P30 to P32 INTP1 to INTP3 Input 1 INTP4 Input 1 TI51 Input 1 P33 TO51 Output 0 0 P70 to P77 KR0 to KR7 Input 1 P120 INTP0 Input 1 PCL Output 0 0 P140 INTP6 Input 1 BUZ Output...

Page 106: ...3 P13 2 P12 1 P11 0 P10 FF01H 00H output latch R W R 7 P27 P2 6 P26 5 P25 4 P24 3 P23 2 P22 1 P21 0 P20 FF02H Undefined 7 0 P3 6 0 5 0 4 0 3 P33 2 P32 1 P31 0 P30 FF03H 00H output latch R W 7 0 P4 6 0 5 0 4 0 3 P43 2 P42 1 P41 0 P40 FF04H 00H output latch R W 7 0 P5 6 0 5 0 4 0 3 P53 2 P52 1 P51 0 P50 FF05H 00H output latch R W 7 0 P6 6 0 5 0 4 0 3 P63 2 P62 1 P61 0 P60 FF06H 00H output latch R W ...

Page 107: ...2 and PU14 These registers can be set by a 1 bit or 8 bit memory manipulation instruction RESET input clears these registers to 00H Figure 4 23 Format of Pull up Resistor Option Register 7 0 Symbol PU0 6 PU06 5 PU05 4 PU04 3 PU03 2 PU02 1 PU01 0 PU00 Address FF30H After reset 00H R W R W 7 PU17 PU1 6 PU16 5 PU15 4 PU14 3 PU13 2 PU12 1 PU11 0 PU10 FF31H 00H R W 7 0 PU3 6 0 5 0 4 0 3 PU33 2 PU32 1 P...

Page 108: ... written to the output latch by a transfer instruction but since the output buffer is off the pin status does not change Once data is written to the output latch it is retained until data is written to the output latch again 4 4 2 Reading from I O port 1 Output mode The output latch contents are read by a transfer instruction The output latch contents do not change 2 Input mode The pin status is r...

Page 109: ...ystem clock oscillator The subsystem clock oscillator oscillates a clock of fXT 32 768 kHz Oscillation cannot be stopped When subsystem clock oscillator is not used setting not to use the on chip feedback resistor is possible using the processor clock control register PCC and the operating current can be reduced in the STOP mode Remarks 1 fXP High speed system clock oscillation frequency 2 fR Ring...

Page 110: ...ain OSC control register MOC Internal bus Ring OSC oscillator Option byte RINGOSC 1 Cannot be stopped 0 Can be stopped CPU clock fCPU Controller Processor clock control register PCC Main clock mode register MCM Oscillation stabilization time counter Oscillation stabilization time select register OSTS Oscillation stabilization time counter status register OSTC Clock to peripheral hardware Prescaler...

Page 111: ...ion time select register OSTS 1 Processor clock control register PCC The PCC register is used to select the CPU clock the division ratio main system clock oscillator operation stop and whether to use the on chip feedback resistorNote of the subsystem clock oscillator The PCC is set by a 1 bit or 8 bit memory manipulation instruction RESET input clears PCC to 00H Note The feedback resistor is requi...

Page 112: ...used to stop the high speed system clock oscillator operation When the CPU is operating on the Ring OSC clock use bit 7 MSTOP of the main OSC control register MOC to stop the high speed system clock oscillator operation this cannot be set by MCC A STOP instruction should not be used 3 Clear this bit to 0 when the subsystem clock is used and set it to 1 when the subsystem clock is not used 4 Be sur...

Page 113: ...X 0 2 µs 0 125 µs 8 3 µs TYP fX 2 0 4 µs 0 25 µs 16 6 µs TYP fX 2 2 0 8 µs 0 5 µs Setting prohibited fX 2 3 1 6 µs 1 0 µs Setting prohibited fX 2 4 3 2 µs 2 0 µs Setting prohibited fXT 2 122 1 µs Note The main clock mode register MCM is used to set the CPU clock high speed system clock Ring OSC clock see Figure 5 4 2 Ring OSC mode register RCM This register sets the operation mode of Ring OSC This...

Page 114: ...OSC oscillator output fX is supplied to the peripheral hardware fX 240 kHz TYP Operation of the peripheral hardware with Ring OSC clock cannot be guaranteed Therefore when Ring OSC clock is selected as the clock supplied to the CPU do not use peripheral hardware In addition stop the peripheral hardware before switching the clock supplied to the CPU from the high speed system clock to the Ring OSC ...

Page 115: ...tion instruction RESET input clears this register to 00H Figure 5 5 Format of Main OSC Control Register MOC Address FFA2H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 MOC MSTOP 0 0 0 0 0 0 0 MSTOP Control of high speed system clock oscillator operation 0 High speed system clock oscillator operating 1 High speed system clock oscillator stopped Cautions 1 Make sure that bit 1 MCS of the main clock mod...

Page 116: ...0 0 0 2 13 fXP min 819 2 µs min 512 µs min 1 1 1 0 0 2 14 fXP min 1 64 ms min 1 02 ms min 1 1 1 1 0 2 15 fXP min 3 27 ms min 2 04 ms min 1 1 1 1 1 2 16 fXP min 6 55 ms min 4 09 ms min Cautions 1 After the above time has elapsed the bits are set to 1 in order from MOST11 and remain 1 2 If the STOP mode is entered and then released while the Ring OSC is being used as the CPU clock set the oscillatio...

Page 117: ...0 2 15 fXP 3 27 ms 2 04 ms 1 0 1 2 16 fXP 6 55 ms 4 09 ms Other than above Setting prohibited Cautions 1 To set the STOP mode when the high speed system clock is used as the CPU clock set OSTS before executing a STOP instruction 2 Before setting OSTS confirm with OSTC that the desired oscillation stabilization time has elapsed 3 If the STOP mode is entered and then released while the Ring OSC is b...

Page 118: ...peed System Clock Oscillator a Crystal ceramic oscillation b External clock VSS X1 X2 Crystal resonator or ceramic resonator External clock X1 X2 Cautions are listed on the next page 5 4 2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator Standard 32 768 kHz connected to the XT1 and XT2 pins External clocks can be input to the subsystem clock oscillator ...

Page 119: ...ng current flows Always make the ground point of the oscillator capacitor the same potential as VSS Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals from the oscillator Note that the subsystem clock oscillator is designed as a low amplitude circuit for reducing power consumption Figure 5 10 shows examples of incorrect resonator connection Figu...

Page 120: ...alternating current d Current flowing through ground line of oscillator potential at points A B and C fluctuates VSS X1 X2 VSS X1 X2 A B C Pmn VDD High current High current e Signals are fetched VSS X1 X2 Remark When using the subsystem clock replace X1 and X2 with XT1 and XT2 respectively Also insert resistors in series on the XT2 side ...

Page 121: ...eedback resistor is required to control the bias point of the oscillation waveform so that the bias point is in the middle of the power supply voltage 5 4 4 Ring OSC oscillator A Ring OSC oscillator is incorporated in the 78K0 KE1 Can be stopped by software or Cannot be stopped can be selected using the option byte The Ring OSC oscillator always oscillates the Ring OSC clock after RESET release 24...

Page 122: ...ice cannot operate if the high speed system clock is damaged or badly connected and therefore does not operate after reset is released However the start clock of the CPU is the on chip Ring OSC clock so the device can be started by the Ring OSC clock after reset release by the clock monitor detection of high speed system clock stop Consequently the system can be safely shut down by performing a mi...

Page 123: ...register OSTC before switching the CPU clock The CPU clock status can be checked using bit 1 MCS of MCM c Ring OSC can be set to stopped oscillating using the Ring OSC mode register RCM when Can be stopped by software is selected for the Ring OSC by the option byte if the high speed system or subsystem clock is used as the CPU clock Make sure that MCS is 1 at this time d When Ring OSC is used as t...

Page 124: ...e Interrupt Interrupt HALT instruction STOP instruction STOP instruction STOP instruction STOP instruction RSTOP 0 RSTOP 1Note 1 MCM0 0 MCM0 1Note 2 MSTOP 1Note 3 MSTOP 0 HALT instruction HALT instruction HALT instruction STOPNote 4 ResetNote 5 Notes 1 When shifting from status 3 to status 4 make sure that bit 1 MCS of the main clock mode register MCM is 1 2 Before shifting from status 2 to status...

Page 125: ... CPU clock fXT fXP Oscillation stopped fR Oscillating oscillation stopped Status 5 CPU clock fXT fXP Oscillating fR Oscillating oscillation stopped Notes 1 When shifting from status 3 to status 4 make sure that bit 1 MCS of the main clock mode register MCM is 1 2 Before shifting from status 2 to status 3 after reset and STOP are released check the high speed system clock oscillation stabilization ...

Page 126: ... Reset release Notes 1 Before shifting from status 2 to status 3 after reset and STOP are released check the high speed system clock oscillation stabilization time status using the oscillation stabilization time counter status register OSTC 2 When shifting from status 2 to status 1 make sure that MCS is 0 3 The watchdog timer operates using Ring OSC even in STOP mode if Ring OSC cannot be stopped ...

Page 127: ... fR Oscillating Status 4 CPU clock fXT fXP Oscillating fR Oscillating Notes 1 Before shifting from status 2 to status 3 after reset and STOP are released check the high speed system clock oscillation stabilization time status using the oscillation stabilization time counter status register OSTC 2 When shifting from status 2 to status 1 make sure that MCS is 0 3 The watchdog timer operates using Ri...

Page 128: ...C by the option byte Remark MSTOP Bit 7 of the main OSC control register MOC MCC Bit 7 of the processor clock control register PCC RSTOP Bit 0 of the Ring OSC mode register RCM MCM0 Bit 0 of the main clock mode register MCM Table 5 4 Oscillation Control Flags and Clock Oscillation Status High Speed System Clock Oscillator Ring OSC Oscillator RSTOP 0 Stopped Oscillating MSTOP 1 Note RSTOP 1 Setting...

Page 129: ...rmed using either the Ring OSC clock or high speed system clock To stop the original clock after switching the clock wait for the number of clocks shown in Table 5 5 before stopping Table 5 5 Time Required to Switch Between Ring OSC Clock and High Speed System Clock PCC Time Required for Switching PCC2 PCC1 PCC0 High Speed System Clock Ring OSC Ring OSC High Speed System Clock 0 0 0 fXP fR 1 clock...

Page 130: ... clocks fXP fXT clocks 489 clocks 0 0 1 8 clocks 8 clocks 8 clocks 8 clocks fXP 2fXT clocks 245 clocks 0 1 0 4 clocks 4 clocks 4 clocks 4 clocks fXP 4fXT clocks 123 clocks 0 1 1 2 clocks 2 clocks 2 clocks 2 clocks fXP 8fXT clocks 62 clocks 0 1 0 0 1 clock 1 clock 1 clock 1 clock fXP 16fXT clocks 31 clocks 1 1 clock 1 clock 1 clock 1 clock 1 clock Cautions 1 Selection of the CPU clock cycle divisio...

Page 131: ...ation stabilization time has elapsed High speed system clock oscillation stabilization time has not elapsed PCC 00H RCM 00H MCM 00H MOC 00H OSTC 00H OSTS 05HNote OSTC checkNote Each processing After reset PCC setting MCM 0 1 High speed system clock operation Ring OSC clock operation dividing set PCC Register value after reset Ring OSC clock operation High speed system clock operation Note Check th...

Page 132: ... Ring OSC oscillating Ring OSC clock operation High speed system clock oscillation High speed system clock or Ring OSC clock High speed system clock operation No RSTOP 0 Yes RSTOP 1 PCC 7 MCC 0 PCC 4 CSS 0 MCM 03H RCM 0Note RSTOP 1 RSTOP 0 MCM 0 0 Register setting in high speed system clock operation High speed system clock operation Ring OSC clock operation Note Required only when can be stopped ...

Page 133: ...S is changed from 0 to 1 Subsystem clock operation Subsystem clock operation High speed system clock oscillation High speed system clock or Ring OSC clock High speed system clock operation PCC 7 MCC 0 PCC 4 CSS 0 MCM 03H CSS 1Note Register setting in high speed system clock operation High speed system clock operation Subsystem clock Note Set CSS to 1 after confirming that oscillation of the subsys...

Page 134: ...led Wait for high speed system clock oscillation stabilization time High speed system clock operation CLS is changed from 1 to 0 MCS 1 not changed High speed system clock oscillation stabilization time elapsed High speed system clock oscillation stabilization time not elapsed Yes High speed system clock oscillation stopped No High speed system clock oscillating MCC 0 PCC 4 CSS 1 MCM 03H MCC 1 OSTC...

Page 135: ...m clock Note 4 High speed system clock stopped Ring OSC stopped 1 1 1 Note 5 0 Note 6 1 1 1 Notes 1 Valid only when can be stopped by software is selected for Ring OSC by the option byte 2 Do not set MCC 1 or MSTOP 1 during high speed system clock operation even if MCC 1 or MSTOP 1 is set the high speed system clock oscillation does not stop 3 Do not set MCC 1 during Ring OSC operation even if MCC...

Page 136: ... interrupt request at the preset time interval 2 PPG output 16 bit timer event counters 00 and 01 can output a rectangular wave whose frequency and output pulse width can be set freely 3 Pulse width measurement 16 bit timer event counters 00 and 01 can measure the pulse width of an externally input signal 4 External event counter 16 bit timer event counters 00 and 01 can measure the number of puls...

Page 137: ...PM0 Port register 0 P0 Remark n 0 µPD78F0132H n 0 1 µPD78F0133H 78F0134H 78F0136H 78F0138H 78F0138HD Figures 6 1 and 6 2 show the block diagrams Figure 6 1 Block Diagram of 16 Bit Timer Event Counter 00 Internal bus Capture compare control register 00 CRC00 TI010 TO00 P01 fX fX 22 fX 28 fX TI000 P00 Prescaler mode register 00 PRM00 2 PRM001 PRM000 CRC002 16 bit timer capture compare register 010 C...

Page 138: ...RM011 PRM010 CRC012 16 bit timer capture compare register 011 CR011 Match Match 16 bit timer counter 01 TM01 Clear Noise elimi nator CRC012CRC011 CRC010 INTTM001 TO01 TI011 P06 INTTM011 16 bit timer output control register 01 TOC01 16 bit timer mode control register 01 TMC01 Internal bus TMC013 TMC012 TMC011OVF01 TOC014LVS01 LVR01 TOC011TOE01 Selector 16 bit timer capture compare register 001 CR00...

Page 139: ...ture compare register 00n CR00n CR00n is a 16 bit register that has the functions of both a capture register and a compare register Whether it is used as a capture register or as a compare register is set by bit 0 CRC0n0 of capture compare control register 0n CRC0n CR00n can be set by a 16 bit memory manipulation instruction RESET input clears this register to 0000H Figure 6 4 Format of 16 Bit Tim...

Page 140: ...C0n 3 n 0 µPD78F0132H n 0 1 µPD78F0133H 78F0134H 78F0136H 78F0138H 78F0138HD Cautions 1 Set a value other than 0000H in CR00n in the mode in which clear start occurs on a match of TM0n and CR00n 2 If CR00n is cleared to 0000H in the free running mode and in the clear mode using the valid edge of the TI00n pin an interrupt request INTTM00n is generated when the value of CR00n changes from 0000H to ...

Page 141: ...n valid edge is set by prescaler mode register 0n PRM0n see Table 6 3 Table 6 3 CR01n Capture Trigger and Valid Edge of TI00n Pin CRC0n2 1 TI00n Pin Valid Edge CR01n Capture Trigger ES0n1 ES0n0 Falling edge Falling edge 0 0 Rising edge Rising edge 0 1 Both rising and falling edges Both rising and falling edges 1 1 Remarks 1 Setting ES0n1 ES0n0 1 0 is prohibited 2 ES0n1 ES0n0 Bits 5 and 4 of presca...

Page 142: ...ode register 0 PM0 Port register 0 P0 1 16 bit timer mode control register 0n TMC0n This register sets the 16 bit timer operating mode the 16 bit timer counter 0n TM0n clear mode and output timing and detects an overflow TMC0n can be set by a 1 bit or 8 bit memory manipulation instruction RESET input clears TMC0n to 00H Caution 16 bit timer counter 0n TM0n starts operation at the moment TMC0n2 and...

Page 143: ...tween TM00 and CR010 or TI000 pin valid edge When used as compare register Generated on match between TM00 and CR000 or match between TM00 and CR010 When used as capture register Generated by inputting CR000 capture trigger OVF00 16 bit timer counter 00 TM00 overflow detection 0 Overflow not detected 1 Overflow detected Cautions 1 Timer operation must be stopped before writing to bits other than t...

Page 144: ...tween TM01 and CR011 or TI001 pin valid edge When used as compare register Generated on match between TM01 and CR001 or match between TM01 and CR011 When used as capture register Generated by inputting CR001 capture trigger OVF01 16 bit timer counter 01 TM01 overflow detection 0 Overflow not detected 1 Overflow detected Cautions 1 Timer operation must be stopped before writing to bits other than t...

Page 145: ...ates as capture register CRC001 CR000 capture trigger selection 0 Captures on valid edge of TI010 pin 1 Captures on valid edge of TI000 pin by reverse phase Note CRC000 CR000 operating mode selection 0 Operates as compare register 1 Operates as capture register Note The capture operation is not performed if both the rising and falling edges are specified as the valid edge of the TI000 pin Cautions...

Page 146: ... before setting CRC01 2 When the mode in which clear start occurs on a match between TM01 and CR001 is selected with 16 bit timer mode control register 01 TMC01 CR001 should not be specified as a capture register 3 To ensure that the capture operation is performed properly the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 01 PRM01 3 ...

Page 147: ...ration TOE00 Timer output control 0 Disables output output fixed to level 0 1 Enables output Note The one shot pulse output mode operates correctly only in the free running mode and the mode in which clear start occurs at the TI000 pin valid edge In the mode in which clear start occurs on a match between the TM00 register and CR000 register one shot pulse output is not possible because an overflow...

Page 148: ...ration TOE01 Timer output control 0 Disables output output fixed to level 0 1 Enables output Note The one shot pulse output mode operates correctly only in the free running mode and the mode in which clear start occurs at the TI001 pin valid edge In the mode in which clear start occurs on a match between the TM01 register and CR001 register one shot pulse output is not possible because an overflow...

Page 149: ...ES001 ES000 0 0 PRM001 PRM000 ES101 ES100 TI010 pin valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges ES001 ES000 TI000 pin valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges PRM001 PRM000 Count clock selection Note 1 0 0 fX 10 MHz 0 1 fX 2 2 2 5 MHz 1 0 fX 2 8 39 06 kHz 1 1 TI0...

Page 150: ...e set for the count clock do not set the clear start mode using the valid edge of the TI000 pin and the capture trigger 4 If the TI000 or TI010 pin is high level immediately after system reset the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge s of the TI000 pin or TI010 pin to enable the operation of 16 bit timer counter 00...

Page 151: ...11 ES010 TI001 pin valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges PRM011 PRM010 Count clock selection Note 1 0 0 fX 10 MHz 0 1 fX 2 4 625 kHz 1 0 fX 2 6 156 25 kHz 1 1 TI001 valid edge Note 2 Notes 1 Be sure to set the count clock so that the following condition is satisfied VDD 4 0 to 5 5 V Count clock 10 MHz VDD 3 3 to 4 0 V Count c...

Page 152: ...01 Care is therefore required when pulling up the TI001 or TI011 pin However if the TI001 or TI011 pin is high level when re enabling operation after the operation has been stopped the rising edge is not detected 5 When the valid edge of the TI011 pin is used P06 cannot be used as the timer output pin TO01 When P06 is used as the TO01 pin the valid edge of the TI011 pin cannot be used Remarks 1 fX...

Page 153: ...MC0n register to start the operation see Figure 6 15 for the set value Caution Do not rewrite CR00n during TM0n operation Remark For how to enable the INTTM00n interrupt see CHAPTER 17 INTERRUPT FUNCTIONS Interrupt requests are generated repeatedly using the count value preset in 16 bit timer capture compare register 00n CR00n as the interval When the count value of 16 bit timer counter 0n TM0n ma...

Page 154: ...n 7 0 6 0 5 0 4 0 3 0 CRC0n2 0 1 CRC0n1 0 1 CRC0n0 0 CRC0n CR00n used as compare register c Prescaler mode register 0n PRM0n ES1n1 0 1 ES1n0 0 1 ES0n1 0 1 ES0n0 0 1 3 0 2 0 PRM0n1 0 1 PRM0n0 0 1 PRM0n Selects count clock Setting invalid setting 10 is prohibited Setting invalid setting 10 is prohibited Remarks 1 0 1 Setting 0 or 1 allows another function to be used simultaneously with the interval ...

Page 155: ... pin names without parentheses are for 16 bit timer event counter 00 and those in parentheses are for 16 bit timer event counter 01 2 OVF0n is set to 1 only when 16 bit timer capture compare register 00n is set to FFFFH Figure 6 17 Timing of Interval Timer Operation Count clock t TM0n count value CR00n INTTM00n 0000H 0001H N 0000H 0001H N 0000H 0001H N N N N N Timer operation enabled Clear Clear I...

Page 156: ...the count clock by using the PRM0n register 6 Set the TMC0n register to start the operation see Figure 6 18 for the set value Caution To change the value of the duty factor the value of the CR01n register during operation see Caution 2 in Figure 6 20 PPG Output Operation Timing Remarks 1 For the setting of the TO0n pin see 6 3 5 Port mode register 0 PM0 2 For how to enable the INTTM00n interrupt s...

Page 157: ...TOE0n 1 TOC0n Enables TO0n output Inverts output on match between TM0n and CR00n Specifies initial value of TO0n output F F setting 11 is prohibited Inverts output on match between TM0n and CR01n Disables one shot pulse output d Prescaler mode register 0n PRM0n ES1n1 0 1 ES1n0 0 1 ES0n1 0 1 ES0n0 0 1 3 0 2 0 PRM0n1 0 1 PRM0n0 0 1 PRM0n Selects count clock Setting invalid setting 10 is prohibited S...

Page 158: ...ing t 0000H 0000H 0001H 0001H M 1 Count clock TM0n count value TO0n Pulse width M 1 t 1 cycle N 1 t N CR00n capture value CR01n capture value M M N 1 N N Clear Clear Cautions 1 Do not rewrite CR00n during TM0n operation 2 In the PPG output operation change the pulse width rewrite CR01n during TM0n operation using the following procedure 1 Disable the timer output inversion operation by match of TM...

Page 159: ...ck cycle selected by prescaler mode register 0n PRM0n and the valid level of the TI00n or TI01n pin is detected twice thus eliminating noise with a short pulse width Figure 6 21 CR01n Capture Operation with Rising Edge Specified Count clock TM0n TI00n Rising edge detection CR01n INTTM01n N 3 N 2 N 1 N N 1 N Setting The basic operation setting procedure is as follows 1 Set the CRC0n register see Fi...

Page 160: ...th a short pulse width Figure 6 22 Control Register Settings for Pulse Width Measurement with Free Running Counter and One Capture Register When TI00n and CR01n Are Used a 16 bit timer mode control register 0n TMC0n 7 0 6 0 5 0 4 0 TMC0n3 0 TMC0n2 1 TMC0n1 0 1 OVF0n 0 TMC0n Free running mode b Capture compare control register 0n CRC0n 7 0 6 0 5 0 4 0 3 0 CRC0n2 1 CRC0n1 0 1 CRC0n0 0 CRC0n CR00n us...

Page 161: ...uencies without parentheses are for 16 bit timer event counter 00 and those in parentheses are for 16 bit timer event counter 01 Figure 6 24 Timing of Pulse Width Measurement Operation with Free Running Counter and One Capture Register with Both Edges Specified t 0000H 0000H FFFFH 0001H D0 D0 Count clock TM0n count value TI00n pin input CR01n capture value INTTM01n OVF0n D1 D0 t D3 D2 t 10000H D1 ...

Page 162: ... Sampling is performed using the count clock cycle selected by prescaler mode register 0n PRM0n and a capture operation is only performed when a valid level of the TI00n or TI01n pin is detected twice thus eliminating noise with a short pulse width Figure 6 25 Control Register Settings for Measurement of Two Pulse Widths with Free Running Counter a 16 bit timer mode control register 0n TMC0n 7 0 6...

Page 163: ...dges Specified t 0000H 0000H FFFFH 0001H D0 D0 TI01n pin input CR00n capture value INTTM01n INTTM00n OVF0n D1 D0 t D3 D2 t 10000H D1 D2 t 10000H D1 D2 1 t D1 D2 1 D1 D2 D2 D3 D0 1 D1 D1 1 D2 1 D2 2 Count clock TM0n count value TI00n pin input CR01n capture value Note Note Clear OVF0n by software Remark n 0 µPD78F0132H n 0 1 µPD78F0133H 78F0134H 78F0136H 78F0138H 78F0138HD ...

Page 164: ...en a valid level of the TI00n pin is detected twice thus eliminating noise with a short pulse width Figure 6 27 Control Register Settings for Pulse Width Measurement with Free Running Counter and Two Capture Registers with Rising Edge Specified a 16 bit timer mode control register 0n TMC0n 7 0 6 0 5 0 4 0 TMC0n3 0 TMC0n2 1 TMC0n1 0 1 OVF0n 0 TMC0n Free running mode b Capture compare control regist...

Page 165: ...d edge to the TI00n pin is detected the count value of 16 bit timer counter 0n TM0n is taken into 16 bit timer capture compare register 01n CR01n and then the pulse width of the signal input to the TI00n pin is measured by clearing TM0n and restarting the count operation Either of two edges rising or falling can be selected using bits 4 and 5 ES0n0 and ES0n1 of prescaler mode register 0n PRM0n Sam...

Page 166: ...r Captures to CR00n at inverse edge to valid edge of TI00n CR01n used as capture register c Prescaler mode register 0n PRM0n ES1n1 0 1 ES1n0 0 1 ES0n1 0 ES0n0 1 3 0 2 0 PRM0n1 0 1 PRM0n0 0 1 PRM0n Selects count clock setting 11 is prohibited Specifies rising edge for pulse width detection Setting invalid setting 10 is prohibited Figure 6 30 Timing of Pulse Width Measurement Operation by Means of R...

Page 167: ...vent counter counts the number of external clock pulses input to the TI00n pin using 16 bit timer counter 0n TM0n TM0n is incremented each time the valid edge specified by prescaler mode register 0n PRM0n is input When the TM0n count value matches the 16 bit timer capture compare register 00n CR00n value TM0n is cleared to 0 and the interrupt request signal INTTM00n is generated Input a value othe...

Page 168: ...ster 0n CRC0n 7 0 6 0 5 0 4 0 3 0 CRC0n2 0 1 CRC0n1 0 1 CRC0n0 0 CRC0n CR00n used as compare register c Prescaler mode register 0n PRM0n ES1n1 0 1 ES1n0 0 1 ES0n1 0 ES0n0 1 3 0 2 0 PRM0n1 1 PRM0n0 1 PRM0n Selects external clock Specifies rising edge for pulse width detection Setting invalid setting 10 is prohibited Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with th...

Page 169: ... counter 0n TM0n Valid edge of TI00n pin INTTM00n Note OVF0n is set to 1 only when CR00n is set to FFFFH Figure 6 33 External Event Counter Operation Timing with Rising Edge Specified TI00n pin input TM0n count value CR00n INTTM00n 0000H 0001H 0002H 0003H 0004H 0005H N 1 N 0000H 0001H 0002H 0003H N Caution When reading the external event counter count value TM0n should be read Remark n 0 µPD78F013...

Page 170: ... the INTTM00n interrupt see CHAPTER 17 INTERRUPT FUNCTIONS A square wave with any selected frequency can be output at intervals determined by the count value preset to 16 bit timer capture compare register 00n CR00n The TO0n pin output status is reversed at intervals determined by the count value preset to CR00n 1 by setting bit 0 TOE0n and bit 1 TOC0n1 of 16 bit timer output control register 0n T...

Page 171: ...d Prescaler mode register 0n PRM0n ES1n1 0 1 ES1n0 0 1 ES0n1 0 1 ES0n0 0 1 3 0 2 0 PRM0n1 0 1 PRM0n0 0 1 PRM0n Selects count clock Setting invalid setting 10 is prohibited Setting invalid setting 10 is prohibited Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with square wave output See the description of the respective control registers for details n 0 µPD78F0132H n 0...

Page 172: ...e TOC0n register to 1 by software By setting the OSPT0n bit to 1 16 bit timer event counter 0n is cleared and started and its output becomes active at the count value N set in advance to 16 bit timer capture compare register 01n CR01n After that the output becomes inactive at the count value M set in advance to 16 bit timer capture compare register 00n CR00n Note Even after the one shot pulse has ...

Page 173: ...ster 0n TOC0n 0 7 0 1 1 0 1 TOC0n LVR0n LVS0n TOC0n4 OSPE0n OSPT0n TOC0n1 TOE0n Enables TO0n output Inverts output upon match between TM0n and CR00n Specifies initial value of TO0n output F F setting 11 is prohibited Inverts output upon match between TM0n and CR01n Sets one shot pulse output mode Set to 1 for output 0 1 1 1 d Prescaler mode register 0n PRM0n 0 1 0 1 0 1 0 1 0 PRM0n PRM0n1 PRM0n0 S...

Page 174: ...in Figure 6 38 and by using the valid edge of the TI00n pin as an external trigger The valid edge of the TI00n pin is specified by bits 4 and 5 ES0n0 ES0n1 of prescaler mode register 0n PRM0n The rising falling or both the rising and falling edges can be specified When the valid edge of the TI00n pin is detected the 16 bit timer event counter is cleared and started and the output becomes active at...

Page 175: ... timer output control register 0n TOC0n 0 7 0 1 1 0 1 TOC0n LVR0n TOC0n1 TOE0n OSPE0n OSPT0n TOC0n4 LVS0n Enables TO0n output Inverts output upon match between TM0n and CR00n Specifies initial value of TO0n output F F setting 11 is prohibited Inverts output upon match between TM0n and CR01n Sets one shot pulse output mode 0 1 1 1 d Prescaler mode register 0n PRM0n 0 1 0 1 0 1 PRM0n PRM0n1 PRM0n0 S...

Page 176: ... 1 N 2 M 1 M 2 M 2 M 1 0001H 0000H Count clock TM0n count value CR01n set value CR00n set value TI00n pin input INTTM01n INTTM00n TO0n pin output When TMC0n is set to 08H TM0n count starts t Caution 16 bit timer counter 0n starts operating as soon as a value other than 00 operation stop mode is set to the TMC0n3 and TMC0n2 bits Remark N M n 0 µPD78F0132H n 0 1 µPD78F0133H 78F0134H 78F0136H 78F0138...

Page 177: ...dge setting Set the valid edge of the TI00n pin after setting bits 2 and 3 TMC0n2 and TMC0n3 of 16 bit timer mode control register 0n TMC0n to 0 0 respectively and then stopping timer operation The valid edge is set using bits 4 and 5 ES0n0 and ES0n1 of prescaler mode register 0n PRM0n 5 Re triggering one shot pulse a One shot pulse output by software When a one shot pulse is output do not set the...

Page 178: ... OVF0n flag is cleared before the next count clock is counted before TM0n becomes 0001H after the occurrence of TM0n overflow the OVF0n flag is re set newly so this clear is not valid 7 Conflicting operations When a read period of the 16 bit timer capture compare register CR00n CR01n and a capture trigger input CR00n CR01n used as capture register conflict the priority is given to the capture trig...

Page 179: ...e of the count clock An interrupt request input INTTM00n INTTM01n however is generated at the rise of the next count clock 10 Compare operation A capture operation may not be performed for CR00n CR01n set in compare mode even if a capture trigger has been input 11 Edge detection 1 If the TI00n or TI01n pin is high level immediately after system reset and the rising edge or both the rising and fall...

Page 180: ... 1 Block Diagram of 8 Bit Timer Event Counter 50 Internal bus 8 bit timer compare register 50 CR50 TI50 TO50 FLMD1 P17 fX 22 fX 26 fX 28 fX 213 fX fX 2 Match Mask circuit OVF Clear 3 Selector TCL502 TCL501 TCL500 Timer clock selection register 50 TCL50 Internal bus TCE50 TMC506 LVS50 LVR50 TMC501 TOE50 Invert level 8 bit timer mode control register 50 TMC50 S R S Q R INV Selector To TMH0 To UART0 ...

Page 181: ...8 fX 212 fX fX 2 Match Mask circuit OVF Clear 3 Selector TCL512 TCL511 TCL510 Timer clock selection register 51 TCL51 Internal bus TCE51 TMC516 LVS51 LVR51 TMC511 TOE51 Invert level 8 bit timer mode control register 51 TMC51 S R S Q R INV Selector INTTM51 TO51 TI51 P33 INTP4 Note 1 Note 2 Selector 8 bit timer counter 51 TM51 Selector Output latch P33 PM33 fX 26 fX 24 Notes 1 Timer output F F 2 PWM...

Page 182: ...5n TCL5n 8 bit timer mode control register 5n TMC5n Port mode register 1 PM1 or port mode register 3 PM3 Port register 1 P1 or port register 3 P3 1 8 bit timer counter 5n TM5n TM5n is an 8 bit register that counts the count pulses and is read only The counter is incremented in synchronization with the rising edge of the count clock Figure 7 3 Format of 8 Bit Timer Counter 5n TM5n Symbol TM5n n 0 1...

Page 183: ...he TO5n pin becomes active due to a TM5n overflow and the values of TM5n and CR5n match the TO5n pin becomes inactive The value of CR5n can be set within 00H to FFH RESET input clears CR5n to 00H Figure 7 4 Format of 8 Bit Timer Compare Register 5n CR5n Symbol CR5n n 0 1 Address FF17H CR50 FF41H CR51 After reset 00H R W Cautions 1 In the mode in which clear start occurs on a match of TM5n and CR5n...

Page 184: ...50 0 0 0 0 0 TCL502 TCL501 TCL500 TCL502 TCL501 TCL500 Count clock selection Note 0 0 0 TI50 pin falling edge 0 0 1 TI50 pin rising edge 0 1 0 fX 10 MHz 0 1 1 fX 2 5 MHz 1 0 0 fX 2 2 2 5 MHz 1 0 1 fX 2 6 156 25 kHz 1 1 0 fX 2 8 39 06 kHz 1 1 1 fX 2 13 1 22 kHz Note Be sure to set the count clock so that the following condition is satisfied VDD 4 0 to 5 5 V Count clock 10 MHz VDD 3 3 to 4 0 V Count...

Page 185: ...k so that the following condition is satisfied VDD 4 0 to 5 5 V Count clock 10 MHz VDD 3 3 to 4 0 V Count clock 8 38 MHz VDD 2 7 to 3 3 V Count clock 5 MHz VDD 2 5 to 2 7 V Count clock 2 5 MHz Cautions 1 When the Ring OSC clock is selected as the clock to be supplied to the CPU the clock of the Ring OSC oscillator is divided and supplied as the count clock If the count clock is the Ring OSC clock ...

Page 186: ...s FF6BH After reset 00H R W Note Symbol 7 6 5 4 3 2 1 0 TMC50 TCE50 TMC506 0 0 LVS50 LVR50 TMC501 TOE50 TCE50 TM50 count operation control 0 After clearing to 0 count operation disabled counter stopped 1 Count operation start TMC506 TM50 operating mode selection 0 Mode in which clear start occurs on a match between TM50 and CR50 1 PWM free running mode LVS50 LVR50 Timer output F F status setting 0...

Page 187: ... 0 In PWM mode TMC516 1 TMC511 Timer F F control Active level selection 0 Inversion operation disabled Active high 1 Inversion operation enabled Active low TOE51 Timer output control 0 Output disabled TM51 output is low level 1 Output enabled Note Bits 2 and 3 are write only Cautions 1 The settings of LVS5n and LVR5n are valid in other than PWM mode 2 Perform 1 to 4 below in the following order no...

Page 188: ...of P17 and P33 at this time may be 0 or 1 PM1 and PM3 can be set by a 1 bit or 8 bit memory manipulation instruction RESET input sets these registers to FFH Figure 7 9 Format of Port Mode Register 1 PM1 Address FF21H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM1n P1n pin I O mode selection n 0 to 7 0 Output mode output buffer on 1 Input mode output buff...

Page 189: ...lock selection register 5n TCL5n Setting 1 Set the registers TCL5n Select the count clock CR5n Compare value TMC5n Stop the count operation select the mode in which clear start occurs on a match of TM5n and CR5n TMC5n 0000 0B Don t care 2 After TCE5n 1 is set the count operation starts 3 If the values of TM5n and CR5n match INTTM5n is generated TM5n is cleared to 00H 4 INTTM5n is generated repeate...

Page 190: ... 7 11 Interval Timer Operation Timing 2 2 b When CR5n 00H t Interval time Count clock TM5n CR5n TCE5n INTTM5n 00H 00H 00H 00H 00H c When CR5n FFH t Count clock TM5n CR5n TCE5n INTTM5n 01 FE FF 00 FE FF 00 FF FF FF Interval time Interrupt acknowledged Interrupt acknowledged Remark n 0 1 ...

Page 191: ...e port mode register PM17 or PM33 Note to 1 TCL5n Select TI5n pin input edge TI5n pin falling edge TCL5n 00H TI5n pin rising edge TCL5n 01H CR5n Compare value TMC5n Stop the count operation select the mode in which clear start occurs on match of TM5n and CR5n disable the timer F F inversion operation disable timer output TMC5n 0000 00B Don t care 2 When TCE5n 1 is set the number of pulses input fr...

Page 192: ...0 TCL5n Select the count clock CR5n Compare value TMC5n Stop the count operation select the mode in which clear start occurs on a match of TM5n and CR5n LVS5n LVR5n Timer Output F F Status Setting 1 0 High level output 0 1 Low level output Timer output F F inversion enabled Timer output enabled TMC5n 00001011B or 00000111B 2 After TCE5n 1 is set the count operation starts 3 The timer output F F is...

Page 193: ...ates as a PWM output when bit 6 TMC5n6 of 8 bit timer mode control register 5n TMC5n is set to 1 The duty pulse determined by the value set to 8 bit timer compare register 5n CR5n is output from TO5n Set the active level width of the PWM pulse to CR5n the active level can be selected with bit 1 TMC5n1 of TMC5n The count clock can be selected with bits 0 to 2 TCL5n0 to TCL5n2 of timer clock selecti...

Page 194: ...ion Note 8 bit timer event counter 50 P17 PM17 8 bit timer event counter 51 P33 PM33 PWM output operation 1 PWM output output from TO5n outputs an inactive level until an overflow occurs 2 When an overflow occurs the active level is output The active level is output until CR5n matches the count value of 8 bit timer counter 5n TM5n 3 After the CR5n matches the count value the inactive level is outp...

Page 195: ...evel Active level 5 t b CR5n 00H Count clock TM5n CR5n TCE5n INTTM5n TO5n Inactive level Inactive level 01H 00H FFH 00H 01H 02H N N 1 FFH 00H 01H 02H M 00H 00H N 2 L t c CR5n FFH TM5n CR5n TCE5n INTTM5n TO5n 01H 00H FFH 00H 01H 02H N N 1 FFH 00H 01H 02H M 00H FFH N 2 Inactive level Active level Inactive level Active level Inactive level t Remarks 1 1 to 3 and 5 in Figure 7 14 a correspond to 1 to ...

Page 196: ...M5n CR5n TCE5n INTTM5n TO5n 1 CR5n change N M N N 1 N 2 FFH 00H 01H M M 1 M 2 FFH 00H 01H 02H M M 1 M 2 N 02H M H 2 t b CR5n value is changed from N to M after clock rising edge of FFH Value is transferred to CR5n at second overflow Count clock TM5n CR5n TCE5n INTTM5n TO5n N N 1 N 2 FFH 00H 01H N N 1 N 2 FFH 00H 01H 02H N 02H N H M M M 1 M 2 1 CR5n change N M 2 t Caution When reading from CR5n bet...

Page 197: ...rt error An error of up to one clock may occur in the time required for a match signal to be generated after timer start This is because 8 bit timer counters 50 and 51 TM50 TM51 are started asynchronously to the count clock Figure 7 16 8 Bit Timer Counter 5n Start Timing Count clock TM5n count value 00H 01H 02H 03H 04H Timer start Remark n 0 1 ...

Page 198: ...it timers H0 and H1 include the following hardware Table 8 1 Configuration of 8 Bit Timers H0 and H1 Item Configuration Timer register 8 bit timer counter Hn Registers 8 bit timer H compare register 0n CMP0n 8 bit timer H compare register 1n CMP1n Timer output TOHn Control registers 8 bit timer H mode register n TMHMDn 8 bit timer H carrier control register 1 TMCYC1 Note Port mode register 1 PM1 P...

Page 199: ... fX 2 fX 22 fX 26 fX 210 1 0 F F R 3 2 PM15 Match Internal bus 8 bit timer H mode register 0 TMHMD0 8 bit timer H compare register 10 CMP10 Decoder Selector Interrupt generator Output controller Level inversion PWM mode signal Timer H enable signal Clear 8 bit timer H compare register 00 CMP00 Output latch P15 8 bit timer event counter 50 output Selector 8 bit timer counter H0 ...

Page 200: ... INTP5 P16 8 bit timer H carrier control register 1 TMCYC1 INTTMH1 INTTM51 Selector fX fX 22 fX 24 fX 26 fX 212 fR 27 Interrupt generator Output controller Level inversion PM16 Output latch P16 1 0 F F R PWM mode signal Carrier generator mode signal Timer H enable signal 3 2 8 bit timer H compare register 01 CMP01 8 bit timer counter H1 Clear RMC1 NRZB1 NRZ1 Reload interrupt control 8 bit timer H ...

Page 201: ...H Compare Register 1n CMP1n Symbol CMP1n n 0 1 Address FF19H CMP10 FF1BH CMP11 After reset 00H R W 7 6 5 4 3 2 1 0 CMP1n can be rewritten during timer count operation An interrupt request signal INTTMHn is generated if the timer count values and CMP1n match after setting CMP1n in carrier generator mode The timer count value is cleared at the same time If the CMP1n value is rewritten during timer o...

Page 202: ...0 and H1 8 bit timer H mode register n TMHMDn 8 bit timer H carrier control register 1 TMCYC1 Note Port mode register 1 PM1 Port register 1 P1 Note 8 bit timer H1 only 1 8 bit timer H mode register n TMHMDn This register controls the mode of timer H This register can be set by a 1 bit or 8 bit memory manipulation instruction RESET input clears this register to 00H Remark n 0 1 ...

Page 203: ... level High level TOLEV0 0 1 Timer output level control in default mode Disables output Enables output TOEN0 0 1 Timer output control Other than above 7 6 5 4 3 2 1 0 Notes 1 Be sure to set the count clock so that the following condition is satisfied VDD 4 0 to 5 5 V Count clock 10 MHz VDD 3 3 to 4 0 V Count clock 8 38 MHz VDD 2 7 to 3 3 V Count clock 5 MHz VDD 2 5 to 2 7 V Count clock 2 5 MHz 2 N...

Page 204: ...guaranteed 2 When TMHE0 1 setting the other bits of TMHMD0 is prohibited 3 In the PWM output mode be sure to set 8 bit timer H compare register 10 CMP10 when starting the timer count operation TMHE0 1 after the timer count operation was stopped TMHE0 0 be sure to set again even if setting the same value to CMP10 Remarks 1 fX High speed system clock oscillation frequency 2 Figures in parentheses ap...

Page 205: ... 0 1 0 1 10 MHz 2 5 MHz 625 kHz 156 25 kHz 2 44 kHz 1 88 kHz TYP Count clock fCNT selectionNote Setting prohibited Other than above Interval timer mode Carrier generator mode PWM output mode Setting prohibited TMMD11 0 0 1 TMMD10 0 1 0 Timer operation mode Low level High level TOLEV1 0 1 Timer output level control in default mode Disables output Enables output TOEN1 0 1 Timer output control Other ...

Page 206: ...ency of TMH1 becomes more than 6 times the count clock frequency of TM51 Remarks 1 fX High speed system clock oscillation frequency 2 fR Ring OSC clock oscillation frequency 3 Figures in parentheses apply to operation at fX 10 MHz fR 240 kHz TYP 2 8 bit timer H carrier control register 1 TMCYC1 This register controls the remote control output and carrier pulse output status of 8 bit timer H1 This ...

Page 207: ...ear PM15 and PM16 and the output latches of P15 and P16 to 0 PM1 can be set by a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to FFH Figure 8 8 Format of Port Mode Register 1 PM1 Address FF21H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM1n P1n pin I O mode selection n 0 to 7 0 Output mode output buffer on 1 Input mode ou...

Page 208: ...output from TOHn 1 Usage Generates the INTTMHn signal repeatedly at the same interval 1 Set each register Figure 8 9 Register Setting During Interval Timer Square Wave Output Operation i Setting timer H mode register n TMHMDn 0 0 1 0 1 0 1 0 0 0 1 0 1 TMMDn0 TOLEVn TOENn CKSn1 CKSn2 TMHEn TMHMDn CKSn0 TMMDn1 Timer output setting Timer output level inversion setting Interval timer mode setting Coun...

Page 209: ...timer counter Hn clear 2 Level inversion match interrupt occurrence 8 bit timer counter Hn clear 3 1 1 The count operation is enabled by setting the TMHEn bit to 1 The count clock starts counting no more than 1 clock after the operation is enabled 2 When the values of 8 bit timer counter Hn and the CMP0n register match the value of 8 bit timer counter Hn is cleared the TOHn output level is inverte...

Page 210: ...Output Operation 2 2 b Operation when CMP0n FFH 00H Count clock Count start 8 bit timer counter Hn CMP0n TMHEn INTTMHn TOHn 01H FEH Clear Clear FFH 00H FEH FFH 00H FFH Interval time c Operation when CMP0n 00H Count clock Count start 8 bit timer counter Hn CMP0n TMHEn INTTMHn TOHn 00H 00H Interval time Remark n 0 1 ...

Page 211: ... cleared to 0 when 8 bit timer counter Hn and the CMP0n register match after the timer count is started TOHn output becomes inactive when 8 bit timer counter Hn and the CMP1n register match 1 Usage In PWM output mode a pulse for which an arbitrary duty and arbitrary cycle can be set is output 1 Set each register Figure 8 11 Register Setting in PWM Output Mode i Setting timer H mode register n TMHM...

Page 212: ...r to the CMP0n register At this time 8 bit timer counter Hn is not cleared and the INTTMHn signal is not generated 5 By performing procedures 3 and 4 repeatedly a pulse with an arbitrary duty can be obtained 6 To stop the count operation set TMHEn 0 If the setting value of the CMP0n register is N the setting value of the CMP1n register is M and the count clock frequency is fCNT the PWM pulse outpu...

Page 213: ... 4 1 The count operation is enabled by setting the TMHEn bit to 1 Start 8 bit timer counter Hn by masking one count clock to count up At this time TOHn output remains inactive when TOLEVn 0 2 When the values of 8 bit timer counter Hn and the CMP0n register match the TOHn output level is inverted the value of 8 bit timer counter Hn is cleared and the INTTMHn signal is output 3 When the values of 8 ...

Page 214: ...CMP0n FFH CMP1n 00H Count clock 8 bit timer counter Hn CMP0n TMHEn INTTMHn TOHn TOLEVn 0 00H 01H FFH 00H 01H 02H FFH 00H FFH 00H 01H 02H CMP1n FFH 00H c Operation when CMP0n FFH CMP1n FEH Count clock 8 bit timer counter Hn CMP0n TMHEn INTTMHn TOHn TOLEVn 0 00H 01H FEH FFH 00H 01H FEH FFH 00H 01H FEH FFH 00H CMP1n FFH FEH Remark n 0 1 ...

Page 215: ...nual U16899EJ2V0UD 215 Figure 8 12 Operation Timing in PWM Output Mode 3 4 d Operation when CMP0n 01H CMP1n 00H Count clock 8 bit timer counter Hn CMP0n TMHEn INTTMHn TOHn TOLEVn 0 01H 00H 01H 00H 01H 00H 00H 01H 00H 01H CMP1n 00H Remark n 0 1 ...

Page 216: ...er counter Hn is cleared the TOHn output becomes active and the INTTMHn signal is output 4 If the CMP1n register value is changed the value is latched and not transferred to the register When the values of 8 bit timer counter Hn and the CMP1n register before the change match the value is transferred to the CMP1n register and the CMP1n register value is changed 2 However three count clocks or more ...

Page 217: ...ompare register 01 CMP01 generates a low level width carrier pulse waveform and 8 bit timer H compare register 11 CMP11 generates a high level width carrier pulse waveform Rewriting the CMP11 register during 8 bit timer H1 operation is possible but rewriting the CMP01 register is prohibited 2 Carrier output control Carrier output is controlled by the interrupt request signal INTTM51 of 8 bit timer...

Page 218: ...low Figure 8 13 Transfer Timing 8 bit timer H1 count clock TMHE1 INTTM51 INTTM5H1 NRZ1 NRZB1 RMC1 1 1 1 0 0 0 1 2 1 The INTTM51 signal is synchronized with the count clock of 8 bit timer H1 and is output as the INTTM5H1 signal 2 The value of the NRZB1 bit is transferred to the NRZ1 bit at the second clock from the rising edge of the INTTM5H1 signal Cautions 1 Do not rewrite the NRZB1 bit again unt...

Page 219: ...led the first compare register to be compared is the CMP01 register When the count value of 8 bit timer counter H1 and the CMP01 register value match the INTTMH1 signal is generated 8 bit timer counter H1 is cleared and at the same time the compare register to be compared with 8 bit timer counter H1 is switched from the CMP01 register to the CMP11 register 5 When the count value of 8 bit timer cou...

Page 220: ...unt operation was stopped TMHE1 0 be sure to set again even if setting the same value to the CMP11 register 2 Set so that the count clock frequency of TMH1 becomes more than 6 times the count clock frequency of TM51 4 Timing chart The carrier output control timing is shown below Cautions 1 Set the values of the CMP01 and CMP11 registers in a range of 01H to FFH 2 In the carrier generator mode thre...

Page 221: ...ue the first INTTMH1 signal is generated the carrier clock signal is inverted and the compare register to be compared with 8 bit timer counter H1 is switched from the CMP01 register to the CMP11 register 8 bit timer counter H1 is cleared to 00H 4 When the count value of 8 bit timer counter H1 matches the CMP11 register value the INTTMH1 signal is generated the carrier clock signal is inverted and ...

Page 222: ...ignal is inverted and the compare register to be compared with 8 bit timer counter H1 is switched from the CMP01 register to the CMP11 register 8 bit timer counter H1 is cleared to 00H 4 When the count value of 8 bit timer counter H1 matches the CMP11 register value the INTTMH1 signal is generated the carrier clock signal is inverted and the compare register to be compared with 8 bit timer counter...

Page 223: ...hes the CMP01 register value 8 bit timer counter H1 is cleared and the INTTMH1 signal is output 3 The CMP11 register can be rewritten during 8 bit timer H1 operation however the changed value L is latched The CMP11 register is changed when the count value of 8 bit timer counter H1 and the CMP11 register value before the change M match 3 4 When the count value of 8 bit timer counter H1 and the CMP1...

Page 224: ... diagram Figure 9 1 Block Diagram of Watch Timer fX 27 fW 24 fW 25 fW 26 fW 27 fW 28 fW 210 fW 211 fW 29 fXT INTWT INTWTI WTM0 WTM1 WTM2 WTM3 WTM4 WTM5 WTM6 WTM7 fW Clear 11 bit prescaler Clear 5 bit counter Watch timer operation mode register WTM Internal bus Selector Selector Selector Selector fWX 24 fWX 25 fWX Remark fX High speed system clock oscillation frequency fXT Subsystem clock oscillati...

Page 225: ...stem clock oscillation frequency fXT Subsystem clock oscillation frequency fW Watch timer clock frequency 2 Interval timer Interrupt requests INTWTI are generated at preset time intervals Table 9 2 Interval Timer Interval Time Interval Time When Operated at fXT 32 768 kHz When Operated at fX 10 MHz 2 4 fW 488 µs 205 µs 2 5 fW 977 µs 410 µs 2 6 fW 1 95 ms 820 µs 2 7 fW 3 91 ms 1 64 ms 2 8 fW 7 81 m...

Page 226: ...rol register Watch timer operation mode register WTM 9 3 Register Controlling Watch Timer The watch timer is controlled by the watch timer operation mode register WTM Watch timer operation mode register WTM This register sets the watch timer count clock enables disables operation prescaler interval time and 5 bit counter operation control WTM is set by a 1 bit or 8 bit memory manipulation instruct...

Page 227: ... 10 fW 1 1 1 2 11 fW WTM3 WTM2 Interrupt time selection 0 0 2 14 fW 0 1 2 13 fW 1 0 2 5 fW 1 1 2 4 fW WTM1 5 bit counter operation control 0 Clear after operation stop 1 Start WTM0 Watch timer operation enable 0 Operation stop clear both prescaler and timer 1 Operation enable Caution Do not change the count clock and interval time by setting bits 4 to 7 WTM4 to WTM7 of WTM during watch timer opera...

Page 228: ...ly operated zero second start can be achieved only for the watch timer by setting WTM1 to 0 In this case however the 11 bit prescaler is not cleared Therefore an error up to 29 1 fW seconds occurs in the first overflow INTWT after zero second start The interrupt request is generated at the following time intervals Table 9 4 Watch Timer Interrupt Time WTM3 WTM2 Interrupt Time Selection When Operate...

Page 229: ... 0 0 2 4 fW 488 µs 205 µs 0 0 1 2 5 fW 977 µs 410 µs 0 1 0 2 6 fW 1 95 ms 820 µs 0 1 1 2 7 fW 3 91 ms 1 64 ms 1 0 0 2 8 fW 7 81 ms 3 28 ms 1 0 1 2 9 fW 15 6 ms 6 55 ms 1 1 0 2 10 fW 31 3 ms 13 1 ms 1 1 1 2 11 fW 62 5 ms 26 2 ms Remark fX High speed system clock oscillation frequency fXT Subsystem clock oscillation frequency fW Watch timer clock frequency Figure 9 3 Operation Timing of Watch Timer ...

Page 230: ... INTWT is generated after the register is set does not exactly match the specification made with bits 2 and 3 WTM2 and WTM3 of WTM Subsequently however the INTWT signal is generated at the specified intervals Figure 9 4 Example of Generation of Watch Timer Interrupt Request INTWT When Interrupt Period 0 5 s It takes 0 515625 seconds max for the first INTWT to be generated 29 1 32768 0 015625 s lon...

Page 231: ...ng Ring OSC Clock Operation During High Speed System Clock Operation 2 11 fR 4 27 ms 2 13 fXP 819 2 µs 2 12 fR 8 53 ms 2 14 fXP 1 64 ms 2 13 fR 17 07 ms 2 15 fXP 3 28 ms 2 14 fR 34 13 ms 2 16 fXP 6 55 ms 2 15 fR 68 27 ms 2 17 fXP 13 11 ms 2 16 fR 136 53 ms 2 18 fXP 26 21 ms 2 17 fR 273 07 ms 2 19 fXP 52 43 ms 2 18 fR 546 13 ms 2 20 fXP 104 86 ms Remarks 1 fR Ring OSC clock oscillation frequency 2 ...

Page 232: ...watchdog timer can be stopped in standby mode Note 2 Notes 1 As long as power is being supplied Ring OSC oscillation cannot be stopped except in the reset period 2 The conditions under which clock supply to the watchdog timer is stopped differ depending on the clock source of the watchdog timer 1 If the clock source is fXP clock supply to the watchdog timer is stopped under the following condition...

Page 233: ...egister WDTM Watchdog timer enable register WDTE Figure 10 1 Block Diagram of Watchdog Timer fR 22 Clock input controller Output controller Internal reset signal WDCS2 Internal bus WDCS1 WDCS0 fXP 24 WDCS3 WDCS4 0 1 1 Selector 16 bit counter or 213 fXP to 220 fXP 211 fR to 218 fR Watchdog timer enable register WDTE Watchdog timer mode register WDTM 3 2 Clear Option byte to set Ring OSC cannot be s...

Page 234: ...DTM Address FF98H After reset 67H R W WDCS4 Note 1 WDCS3 Note 1 Operation clock selection 0 0 Ring OSC clock fR 0 1 High speed system clock fXP 1 Watchdog timer operation stopped Overflow time setting WDCS2 Note 2 WDCS1 Note 2 WDCS0 Note 2 During Ring OSC clock operation During high speed system clock operation 0 0 0 2 11 fR 4 27 ms 2 13 fXP 819 2 µs 0 0 1 2 12 fR 8 53 ms 2 14 fXP 1 64 ms 0 1 0 2 ...

Page 235: ...DCS4 is cleared to 0 In addition the internal reset signal is not generated Remarks 1 fR Ring OSC clock oscillation frequency 2 fXP High speed system clock oscillation frequency 3 Don t care 4 Figures in parentheses apply to operation at fR 480 kHz MAX fXP 10 MHz 2 Watchdog timer enable register WDTE Writing ACH to WDTE clears the watchdog timer counter and starts counting again This register can ...

Page 236: ...chdog Timer Is Operating WDCS4 Is Set to 1 Source Clock to Watchdog Timer Is Stopped Watchdog timer overflows Internal reset signal is generated Internal reset signal is generated Write to WDTM for the second time Internal reset signal is generated Internal reset signal is generated Internal reset signal is not generated and the watchdog timer does not resume operation Internal reset signal is gen...

Page 237: ... mode register WDTM by an 8 bit memory manipulation instructionNotes 1 2 Cycle Set using bits 2 to 0 WDCS2 to WDCS0 3 After the above procedures are executed writing ACH to WDTE clears the count to 0 enabling recounting Notes 1 The operation clock Ring OSC clock cannot be changed If any value is written to bits 3 and 4 WDCS3 WDCS4 of WDTM it is ignored 2 As soon as WDTM is written the counter of t...

Page 238: ...peration stopped Cycle Set using bits 2 to 0 WDCS2 to WDCS0 3 After the above procedures are executed writing ACH to WDTE clears the count to 0 enabling recounting Notes 1 As soon as WDTM is written the counter of the watchdog timer is cleared 2 Set bits 7 6 and 5 to 0 1 1 respectively Do not set the other values 3 If the watchdog timer is stopped by setting WDCS4 and WDCS3 to 1 and respectively a...

Page 239: ...re 10 4 Operation in STOP Mode CPU Clock and WDT Operation Clock High Speed System Clock Watchdog timer Operating Operation stopped Operating fR fXP CPU operation Normal operation STOP Oscillation stabilization time Normal operation Oscillation stopped Oscillation stabilization time set by OSTS register 2 When the CPU clock is the high speed system clock fXP and the watchdog timer operation clock ...

Page 240: ...k WDT Operation Clock High Speed System Clock 1 Timing when counting is started after the oscillation stabilization time set by the oscillation stabilization time select register OSTS has elapsed Watchdog timer Operating Operation stopped Operating fR fXP CPU operation 17 clocks Normal operation Ring OSC clock Clock supply stopped Normal operation Ring OSC clock Oscillation stopped STOP Oscillatio...

Page 241: ...OSC clock Oscillation stopped STOP Oscillation stabilization time set by OSTS register Operating Operation stopped 10 4 4 Watchdog timer operation in HALT mode when Ring OSC can be stopped by software is selected by option byte The watchdog timer stops counting during HALT instruction execution regardless of whether the CPU clock is the high speed system clock fXP Ring OSC clock fR or subsystem cl...

Page 242: ...r CKS is output In addition the buzzer output is intended for square wave output of buzzer frequency selected with CKS Figure 11 1 shows the block diagram of clock output buzzer output controller Figure 11 1 Block Diagram of Clock Output Buzzer Output Controller fX fX 210 to fX 213 fX to fX 27 fXT BZOE BCS1 BCS0 CLOE CLOE BZOE 8 4 PCL INTP6 P140 BUZ BUSY0 INTP7 P141 BCS0 BCS1 Clock controller Pres...

Page 243: ...n register CKS Port mode register 14 PM14 Port register 14 P14 11 3 Register Controlling Clock Output Buzzer Output Controller The following two registers are used to control the clock output buzzer output controller Clock output selection register CKS Port mode register 14 PM14 1 Clock output selection register CKS This register sets output enable disable for clock output PCL and for the buzzer f...

Page 244: ...PCL output enable disable specification 0 Clock division circuit operation stopped PCL fixed to low level 1 Clock division circuit operation enabled PCL output enabled CCS3 CCS2 CCS1 CCS0 PCL output clock selection Note 0 0 0 0 fX 10 MHz 0 0 0 1 fX 2 5 MHz 0 0 1 0 fX 2 2 2 5 MHz 0 0 1 1 fX 2 3 1 25 MHz 0 1 0 0 fX 2 4 625 kHz 0 1 0 1 fX 2 5 312 5 kHz 0 1 1 0 fX 2 6 156 25 kHz 0 1 1 1 fX 2 7 78 125 ...

Page 245: ...he clock pulse is output as the following procedure 1 Select the clock pulse output frequency with bits 0 to 3 CCS0 to CCS3 of the clock output selection register CKS clock pulse output in disabled status 2 Set bit 4 CLOE of CKS to 1 to enable clock output Remark The clock output controller is designed not to output pulses with a small width during output enable disable switching of the clock outp...

Page 246: ...ction is used to detect a voltage drop in a battery The A D conversion result ADCR register value and power fail comparison threshold register PFT value are compared INTAD is generated only when a comparative condition has been matched Figure 12 1 Block Diagram of A D Converter AVREF AVSS INTAD ADCS bit 3 ADS2 ADS1 ADS0 ADCS FR2 FR1 ADCE FR0 Sample hold circuit AVSS Voltage comparator Controller A...

Page 247: ... input signal of the analog input pin selected by the selector when A D conversion is started and holds the sampled analog input voltage value during A D conversion 3 Series resistor string The series resistor string is connected between AVREF and AVSS and generates a voltage to be compared with the analog input signal Figure 12 2 Circuit Configuration of Series Resistor String AVREF AVSS P ch Ser...

Page 248: ...is pin at the same potential as that of the VDD pin even when the A D converter is not used The signal input to ANI0 to ANI7 is converted into a digital signal based on the voltage applied across AVREF and AVSS 9 AVSS pin This is the ground potential pin of the A D converter Always use this pin at the same potential as that of the VSS pin even when the A D converter is not used 10 A D converter mo...

Page 249: ... 288 fX 240 fX 192 fX 144 fX 120 fX 96 fX Setting prohibited FR2 0 0 0 1 1 1 Other than above FR1 0 0 1 0 0 1 FR0 0 1 0 0 1 0 0 1 2 3 4 5 6 7 ADM Address FF28H After reset 00H R W Symbol µ µ µ µ µ µ 28 8 s 24 0 s 19 2 s 14 4 s 12 0 sNote 1 9 6 sNote 1 µ µ µ µ µ µ fX 8 38 MHz fX 10 MHz Boost reference voltage generator operation controlNote 2 Stops operation of reference voltage generator Enables o...

Page 250: ...tage ADCS Conversion operation Conversion operation Conversion stopped Conversion waiting Boost reference voltage generator operating Note Note The time from the rising of the ADCE bit to the falling of the ADCS bit must be 14 µs or longer to stabilize the reference voltage Cautions 1 A D conversion must be stopped before rewriting bits FR0 to FR2 to values other than the identical data 2 For the ...

Page 251: ...ut Channel Specification Register ADS ADS0 ADS1 ADS2 0 0 0 0 0 Analog input channel specification ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ADS0 0 1 0 1 0 1 0 1 ADS1 0 0 1 1 0 0 1 1 ADS2 0 0 0 0 1 1 1 1 0 1 2 3 4 5 6 7 ADS Address FF29H After reset 00H R W Symbol Cautions 1 Be sure to clear bits 3 to 7 of ADS to 0 2 If data is written to ADS a wait cycle is generated Do not write data to ADS when th...

Page 252: ...ipulation instruction RESET input makes ADCR undefined Figure 12 6 Format of A D Conversion Result Register ADCR Symbol Address FF08H FF09H After reset Undefined R FF09H FF08H 0 0 0 0 0 0 ADCR Cautions 1 When writing to the A D converter mode register ADM and analog input channel specification register ADS the contents of ADCR may become undefined Read the conversion result following conversion co...

Page 253: ...PFCM 0 1 0 1 2 3 4 5 6 7 PFM Address FF2AH After reset 00H R W Symbol Caution If data is written to PFM a wait cycle is generated Do not write data to PFM when the CPU is operating on the subsystem clock and the high speed system clock is stopped For details see CHAPTER 32 CAUTIONS FOR WAIT 5 Power fail comparison threshold register PFT The power fail comparison threshold register PFT is a registe...

Page 254: ...log input is greater than 1 2 AVREF the MSB of SAR remains set to 1 If the analog input is smaller than 1 2 AVREF the MSB is reset to 0 8 Next bit 8 of SAR is automatically set to 1 and the operation proceeds to the next comparison The series resistor string voltage tap is selected according to the preset value of bit 9 as described below Bit 9 1 3 4 AVREF Bit 9 0 1 4 AVREF The voltage tap and ana...

Page 255: ...uously until bit 7 ADCS of the A D converter mode register ADM is reset 0 by software If a write operation is performed to one of the ADM analog input channel specification register ADS power fail comparison mode register PFM or power fail comparison threshold register PFT during an A D conversion operation the conversion operation is initialized and if the ADCS bit is set 1 conversion starts agai...

Page 256: ...eturns integer part of value in parentheses VAIN Analog input voltage AVREF AVREF pin voltage ADCR A D conversion result register ADCR value SAR Successive approximation register Figure 12 10 shows the relationship between the analog input voltage and the A D conversion result Figure 12 10 Relationship Between Analog Input Voltage and A D Conversion Result 1023 1022 1021 3 2 1 0 FFC0H FF80H FF40H ...

Page 257: ...DS is started When A D conversion has been completed the result of the A D conversion is stored in the A D conversion result register ADCR and an interrupt request signal INTAD is generated Once the A D conversion has started and when one A D conversion has been completed the next A D conversion operation is immediately started The A D conversion operations are repeated until new data is written t...

Page 258: ...and an interrupt request signal INTAD is generated under the condition specified by bit 6 PFCM of PFM 1 When PFEN 1 and PFCM 0 The higher 8 bits of ADCR and PFT values are compared when A D conversion ends and INTAD is only generated when the higher 8 bits of ADCR PFT 2 When PFEN 1 and PFCM 1 The higher 8 bits of ADCR and PFT values are compared when A D conversion ends and INTAD is only generated...

Page 259: ...s power fail function 1 Set bit 7 PFEN of the power fail comparison mode register PFM 2 Set power fail comparison condition using bit 6 PFCM of PFM 3 Set bit 0 ADCE of the A D converter mode register ADM to 1 4 Select the channel and conversion time using bits 2 to 0 ADS2 to ADS0 of the analog input channel specification register ADS and bits 5 to 3 FR2 to FR0 of ADM 5 Set a threshold value to the...

Page 260: ...verall error in the characteristics table 3 Quantization error When analog values are converted to digital values a 1 2LSB error naturally occurs In an A D converter an analog input voltage in a range of 1 2LSB is converted to the same digital code so a quantization error cannot be avoided Note that the quantization error is not included in the overall error zero scale error full scale error integ...

Page 261: ... and the ideal value Figure 12 15 Zero Scale Error Figure 12 16 Full Scale Error 111 011 010 001 Zero scale error Ideal line 000 0 1 2 3 AVREF Digital output Lower 3 bits Analog input LSB 111 110 101 000 0 AVREF 3 Full scale error Ideal line Analog input LSB Digital output Lower 3 bits AVREF 2 AVREF 1 AVREF Figure 12 17 Integral Linearity Error Figure 12 18 Differential Linearity Error 0 AVREF Dig...

Page 262: ...end of conversion ADCR read has priority After the read operation the new conversion result is written to ADCR 2 Conflict between ADCR write and A D converter mode register ADM write or analog input channel specification register ADS write upon the end of conversion ADM or ADS write has priority ADCR write is not performed nor is the conversion end interrupt signal INTAD generated 4 Noise counterm...

Page 263: ...converter the internal sampling capacitor is charged and sampling is performed for approx one sixth of the conversion time Since only the leakage current flows other than during sampling and the current for charging the capacitor also flows during sampling the input impedance fluctuates and has no meaning To perform sufficient sampling however it is recommended to make the output impedance of the ...

Page 264: ...n A D conversion ADCR ADIF ANIn ANIn ANIm ANIm ANIn ANIn ANIm ANIm ADS rewrite start of ANIm conversion ADIF is set but ANIm conversion has not ended Remarks 1 n 0 to 7 2 m 0 to 7 9 Conversion results just after A D conversion start The first A D conversion value immediately after A D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 14 µs after the ADCE bit...

Page 265: ... INTAD ADCS 1 or ADS rewrite Sampling time Table 12 3 A D Converter Sampling Time and A D Conversion Start Delay Time ADM Set Value A D Conversion Start Delay Time Note FR2 FR1 FR0 Conversion Time Sampling Time MIN MAX 0 0 0 288 fX 40 fX 32 fX 36 fX 0 0 1 240 fX 32 fX 28 fX 32 fX 0 1 0 192 fX 24 fX 24 fX 28 fX 1 0 0 144 fX 20 fX 16 fX 18 fX 1 0 1 120 fX 16 fX 14 fX 16 fX 1 1 0 96 fX 12 fX 12 fX 14...

Page 266: ...Figure 12 22 Internal Equivalent Circuit of ANIn Pin ANIn C1 C2 C3 R1 R2 Table 12 4 Resistance and Capacitance Values of Equivalent Circuit Reference Values AVREF R1 R2 C1 C2 C3 2 7 V 12 kΩ 8 kΩ 8 pF 3 pF 0 6 pF 4 5 V 4 kΩ 2 7 kΩ 8 pF 1 4 pF 0 6 pF Remarks 1 The resistance and capacitance values shown in Table 12 4 are not guaranteed values 2 n 0 to 7 ...

Page 267: ...Four operating clock inputs selectable Fixed to LSB first communication Cautions 1 If clock supply to serial interface UART0 is not stopped e g in the HALT mode normal operation continues If clock supply to serial interface UART0 is stopped e g in the STOP mode each register stops operating and holds the value immediately before clock supply was stopped The TXD0 pin also holds the value immediatel...

Page 268: ...ion of Serial Interface UART0 Item Configuration Registers Receive buffer register 0 RXB0 Receive shift register 0 RXS0 Transmit shift register 0 TXS0 Control registers Asynchronous serial interface operation mode register 0 ASIM0 Asynchronous serial interface reception error status register 0 ASIS0 Baud rate generator control register 0 BRGC0 Port mode register 1 PM1 Port register 1 P1 ...

Page 269: ...er 0 RXS0 Receive buffer register 0 RXB0 Asynchronous serial interface reception error status register 0 ASIS0 Asynchronous serial interface operation mode register 0 ASIM0 Baud rate generator control register 0 BRGC0 8 bit timer event counter 50 output Registers Selector Baud rate generator Baud rate generator Reception unit Reception control Filter Internal bus Transmission control Transmission ...

Page 270: ...t memory manipulation instruction No data can be written to this register RESET input or POWER0 0 sets this register to FFH 2 Receive shift register 0 RXS0 This register converts the serial data input to the RXD0 pin into parallel data RXS0 cannot be directly manipulated by a program 3 Transmit shift register 0 TXS0 This register is used to set transmit data Transmission is started when data is wr...

Page 271: ...at of Asynchronous Serial Interface Operation Mode Register 0 ASIM0 1 2 Address FF70H After reset 01H R W Symbol 7 6 5 4 3 2 1 0 ASIM0 POWER0 TXE0 RXE0 PS01 PS00 CL0 SL0 1 POWER0 Enables disables operation of internal operation clock 0 Note 1 Disables operation of the internal operation clock fixes the clock to low level and asynchronously resets the internal circuit Note 2 1 Enables operation of ...

Page 272: ...ur Cautions 1 At startup set POWER0 to 1 and then set TXE0 to 1 To stop the operation clear TXE0 to 0 and then clear POWER0 to 0 2 At startup set POWER0 to 1 and then set RXE0 to 1 To stop the operation clear RXE0 to 0 and then clear POWER0 to 0 3 Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0 pin If POWER0 is set to 1 and RXE0 is set to 1 while a low level is input...

Page 273: ...ty bit on completion of reception FE0 Status flag indicating framing error 0 If POWER0 0 and RXE0 0 or if ASIS0 register is read 1 If the stop bit is not detected on completion of reception OVE0 Status flag indicating overrun error 0 If POWER0 0 and RXE0 0 or if ASIS0 register is read 1 If receive data is set to the RXB0 register and the next reception operation is completed before the data is rea...

Page 274: ...0 1 0 0 0 8 fXCLK0 8 0 1 0 0 1 9 fXCLK0 9 0 1 0 1 0 10 fXCLK0 10 1 1 0 1 0 26 fXCLK0 26 1 1 0 1 1 27 fXCLK0 27 1 1 1 0 0 28 fXCLK0 28 1 1 1 0 1 29 fXCLK0 29 1 1 1 1 0 30 fXCLK0 30 1 1 1 1 1 31 fXCLK0 31 Notes 1 Be sure to set the base clock so that the following condition is satisfied VDD 4 0 to 5 5 V Base clock 10 MHz VDD 3 3 to 4 0 V Base clock 8 38 MHz VDD 2 7 to 3 3 V Base clock 5 MHz VDD 2 5 ...

Page 275: ...4 to MDL00 bits k 8 9 10 31 4 Don t care 5 Figures in parentheses apply to operation at fX 10 MHz 6 TMC506 Bit 6 of 8 bit timer mode control register 50 TMC50 TMC501 Bit 1 of TMC50 4 Port mode register 1 PM1 This register sets port 1 input output in 1 bit units When using the P10 TxD0 SCK10 pin for serial interface data output clear PM10 to 0 and set the output latch of P10 to 1 When using the P11...

Page 276: ... 4 3 2 1 0 ASIM0 POWER0 TXE0 RXE0 PS01 PS00 CL0 SL0 1 POWER0 Enables disables operation of internal operation clock 0 Note 1 Disables operation of the internal operation clock fixes the clock to low level and asynchronously resets the internal circuit Note 2 TXE0 Enables disables transmission 0 Disables transmission synchronously resets the transmission circuit RXE0 Enables disables reception 0 Di...

Page 277: ...13 2 3 Set bit 7 POWER0 of the ASIM0 register to 1 4 Set bit 6 TXE0 of the ASIM0 register to 1 Transmission is enabled Set bit 5 RXE0 of the ASIM0 register to 1 Reception is enabled 5 Write data to the TXS0 register Data transmission is started Caution Take relationship with the other party of communication when setting the port mode register and port register The relationship between the register...

Page 278: ...irst Parity bit Even parity odd parity 0 parity or no parity Stop bit 1 or 2 bits The character bit length parity and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 0 ASIM0 Figure 13 7 Example of Normal UART Transmit Receive Data Waveform 1 Data length 8 bits Parity Even parity Stop bit 1 bit Communication data 55H 1 data frame Start D0 D1 ...

Page 279: ...ive data including the parity bit is counted If it is odd a parity error occurs ii Odd parity Transmission Unlike even parity transmit data including the parity bit is controlled so that the number of bits that are 1 is odd If transmit data has an odd number of bits that are 1 0 If transmit data has an even number of bits that are 1 1 Reception The number of bits that are 1 in the receive data inc...

Page 280: ...ng from the LSB When transmission is completed the parity and stop bits set by ASIM0 are appended and a transmission completion interrupt request INTST0 is generated Transmission is stopped until the data to be transmitted next is written to TXS0 Figure 13 8 shows the timing of the transmission completion interrupt request INTST0 This interrupt occurs as soon as the last stop bit has been output C...

Page 281: ...p bit has been received the reception completion interrupt INTSR0 is generated and the data of RXS0 is written to receive buffer register 0 RXB0 If an overrun error OVE0 occurs however the receive data is not written to RXB0 Even if a parity error PE0 occurs while reception is in progress reception continues to the reception position of the stop bit and an error interrupt INTSR0 is generated after...

Page 282: ...Reception Error Reception Error Cause Parity error The parity specified for transmission does not match the parity of the receive data Framing error Stop bit is not detected Overrun error Reception of the next data is completed before data is read from receive buffer register 0 RXB0 f Noise filter of receive data The RXD0 signal is sampled using the base clock output by the prescaler block If two ...

Page 283: ...0 when bit 7 POWER0 or bit 6 TXE0 of asynchronous serial interface operation mode register 0 ASIM0 is 0 It starts counting when POWER0 1 and TXE0 1 The counter is cleared to 0 when the first data transmitted is written to transmit shift register 0 TXS0 Reception counter This counter stops operation cleared to 0 when bit 7 POWER0 or bit 5 RXE0 of asynchronous serial interface operation mode registe...

Page 284: ...0 register k Value set by the MDL04 to MDL00 bits of the BRGC0 register k 8 9 10 31 b Error of baud rate The baud rate error can be calculated by the following expression Error 1 100 Cautions 1 Keep the baud rate error during transmission to within the permissible error range at the reception destination 2 Make sure that the baud rate error during reception satisfies the range shown in 4 Permissib...

Page 285: ...10417 0 16 3 13 10072 3 15 2 25 10475 0 72 19200 3 8 19531 1 73 2 27 19398 1 03 2 14 18705 2 58 31250 2 20 31250 0 2 17 30809 1 41 38400 2 16 39063 1 73 2 14 38796 2 58 2 27 38796 1 03 76800 2 8 78125 1 73 1 27 77593 1 03 1 14 74821 2 58 115200 1 22 113636 1 36 1 18 116389 1 03 1 9 116389 1 03 153600 1 16 156250 1 73 1 14 149643 2 58 230400 1 11 227273 1 36 1 9 232778 1 03 Remark TPS01 TPS00 Bits ...

Page 286: ...it Bit 0 Bit 1 Bit 7 Parity bit Minimum permissible data frame length Maximum permissible data frame length Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Latch timing Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit As shown in Figure 13 12 the latch timing of the receive data is determined by the counter set by baud rate generator control register 0 BRGC0 after the start bit has been de...

Page 287: ...ssible baud rate error between UART0 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions as follows Table 13 5 Maximum Minimum Permissible Baud Rate Error Division Ratio k Maximum Permissible Baud Rate Error Minimum Permissible Baud Rate Error 8 3 53 3 61 16 4 14 4 19 24 4 34 4 38 31 4 44 4 47 Remarks 1 The permissible error of reception depe...

Page 288: ...smission from 13 to 20 bits More than 11 bits can be identified for synchronous break field reception SBF reception flag provided Cautions 1 The TXD6 output inversion function inverts only the transmission side and not the reception side To use this function the reception side must be ready for reception of inverted data 2 If clock supply to serial interface UART6 is not stopped e g in the HALT mo...

Page 289: ...es it and corrects the baud rate error Therefore communication is possible when the baud rate error in the slave is 15 or less Figures 14 1 and 14 2 outline the transmission and reception operations of LIN Figure 14 1 LIN Transmission Operation Sleep bus Wakeup signal frame 8 bitsNote 1 55H transmission Data transmission Data transmission Data transmission Data transmission 13 bitNote 2 SBF transm...

Page 290: ...This SBF reception completion interrupt enables the capture timer Detection of errors OVE6 PE6 and FE6 is suppressed and error detection processing of UART communication and data transfer of the shift register and RXB6 is not performed The shift register holds the reset value FFH 4 Calculate the baud rate error from the bit length of the synchronous field disable UART6 after SF reception and then ...

Page 291: ...elector Selector Selector Port mode PM00 Output latch P00 Remark ISC0 ISC1 Bits 0 and 1 of the input switch control register ISC see Figure 14 11 The peripheral functions used in the LIN communication operation are shown below Peripheral functions used External interrupt INTP0 wakeup signal detection Use Detects the wakeup signal edges and detects start of communication 16 bit timer event counter ...

Page 292: ...r 6 RXS6 Transmit buffer register 6 TXB6 Transmit shift register 6 TXS6 Control registers Asynchronous serial interface operation mode register 6 ASIM6 Asynchronous serial interface reception error status register 6 ASIS6 Asynchronous serial interface transmission status register 6 ASIF6 Clock selection register 6 CKSR6 Baud rate generator control register 6 BRGC6 Asynchronous serial interface con...

Page 293: ...ister 6 RXB6 RXD6 P14 TI000 INTP0Note INTSR6 Baud rate generator Filter INTSRE6 Asynchronous serial interface reception error status register 6 ASIS6 Asynchronous serial interface operation mode register 6 ASIM6 Asynchronous serial interface transmission status register 6 ASIF6 Transmission control Registers fX fX 2 fX 22 fX 23 fX 24 fX 25 fX 26 fX 27 fX 28 fX 29 fX 210 8 bit timer event counter 5...

Page 294: ...ctly manipulated by a program 3 Transmit buffer register 6 TXB6 This buffer register is used to set transmit data Transmission is started when data is written to TXB6 This register can be read or written by an 8 bit memory manipulation instruction RESET input sets this register to FFH Cautions 1 Do not write data to TXB6 when bit 1 TXBF6 of asynchronous serial interface transmission status registe...

Page 295: ...hen bit 7 POWER6 and bit 6 TXE6 of ASIM6 1 or bit 7 POWER6 and bit 5 RXE6 of ASIM6 1 Figure 14 5 Format of Asynchronous Serial Interface Operation Mode Register 6 ASIM6 1 2 Address FF50H After reset 01H R W Symbol 7 6 5 4 3 2 1 0 ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6 POWER6 Enables disables operation of internal operation clock 0 Note 1 Disables operation of the internal operation clock f...

Page 296: ...r 1 INTSR6 occurs in case of error at this time INTSRE6 does not occur Note If reception as 0 parity is selected the parity is not judged Therefore bit 2 PE6 of asynchronous serial interface reception error status register 6 ASIS6 is not set and the error interrupt does not occur Cautions 1 At startup set POWER6 to 1 and then set TXE6 to 1 To stop the operation clear TXE6 to 0 and then clear POWER...

Page 297: ...arity bit on completion of reception FE6 Status flag indicating framing error 0 If POWER6 0 and RXE6 0 or if ASIS6 register is read 1 If the stop bit is not detected on completion of reception OVE6 Status flag indicating overrun error 0 If POWER6 0 and RXE6 0 or if ASIS6 register is read 1 If receive data is set to the RXB6 register and the next reception operation is completed before the data is ...

Page 298: ...r TXE6 0 or if data is transferred to transmit shift register 6 TXS6 1 If data is written to transmit buffer register 6 TXB6 if data exists in TXB6 TXSF6 Transmit shift register data flag 0 If POWER6 0 or TXE6 0 or if the next data is not transferred from transmit buffer register 6 TXB6 after completion of transfer 1 If data is transferred from transmit buffer register 6 TXB6 if data transmission ...

Page 299: ... 2 10 9 77 kHz 1 0 1 1 TM50 output Note 2 Other than above Setting prohibited Notes 1 Be sure to set the base clock so that the following condition is satisfied VDD 4 0 to 5 5 V Base clock 10 MHz VDD 3 3 to 4 0 V Base clock 8 38 MHz VDD 2 7 to 3 3 V Base clock 5 MHz VDD 2 5 to 2 7 V Base clock 2 5 MHz 2 Note the following points when selecting the TM50 output as the base clock PWM mode TMC506 1 St...

Page 300: ...t 5 RXE6 of ASIM6 1 Figure 14 9 Format of Baud Rate Generator Control Register 6 BRGC6 Address FF57H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 BRGC6 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 k Output clock selection of 8 bit counter 0 0 0 0 0 Setting prohibited 0 0 0 0 1 0 0 0 8 fXCLK6 8 0 0 0 0 1 0 0 1 9 fXCLK6 9 0 0 0 0 1 0 1 0 10 fXCLK6 10 ...

Page 301: ...and bit 5 RXE6 of ASIM6 1 Note however that communication is started by the refresh operation because bit 6 SBRT6 of ASICL6 is cleared to 0 when communication is completed when an interrupt signal is generated Figure 14 10 Format of Asynchronous Serial Interface Control Register 6 ASICL6 1 2 Address FF58H After reset 16H R W Note Symbol 7 6 5 4 3 2 1 0 ASICL6 SBRF6 SBRT6 SBTT6 SBL62 SBL61 SBL60 DI...

Page 302: ...put of TXD6 1 Inverted output of TXD6 Cautions 1 In the case of an SBF reception error return the mode to the SBF reception mode The status of the SBRF6 flag is held 1 2 Before setting the SBRT6 bit make sure that bit 7 POWER6 and bit 5 RXE6 of ASIM6 1 3 The read value of the SBRT6 bit is always 0 SBRT6 is automatically cleared to 0 after SBF reception has been correctly completed 4 Before setting...

Page 303: ...urce selection 0 TI000 P00 1 RxD6 P14 ISC0 INTP0 input source selection 0 INTP0 P120 1 RxD6 P14 8 Port mode register 1 PM1 This register sets port 1 input output in 1 bit units When using the P13 TxD6 pin for serial interface data output clear PM13 to 0 and set the output latch of P13 to 1 When using the P14 RxD6 pin for serial interface data input set PM14 to 1 The output latch of P14 at this tim...

Page 304: ...les operation of internal operation clock 0 Note 1 Disables operation of the internal operation clock fixes the clock to low level and asynchronously resets the internal circuit Note 2 TXE6 Enables disables transmission 0 Disables transmission operation synchronously resets the transmission circuit RXE6 Enables disables reception 0 Disables reception synchronously resets the reception circuit Note...

Page 305: ... register 6 BRGC6 Asynchronous serial interface control register 6 ASICL6 Input switch control register ISC Port mode register 1 PM1 Port register 1 P1 The basic procedure of setting an operation in the UART mode is as follows 1 Set the CKSR6 register see Figure 14 8 2 Set the BRGC6 register see Figure 14 9 3 Set bits 0 to 4 ISRM6 SL6 CL6 PS60 PS61 of the ASIM6 register see Figure 14 5 4 Set bits ...

Page 306: ...6 PM13 P13 PM14 P14 UART6 Operation TxD6 P13 RxD6 P14 0 0 0 Note Note Note Note Stop P13 P14 0 1 Note Note 1 Reception P13 RxD6 1 0 0 1 Note Note Transmission TxD6 P14 1 1 1 0 1 1 Transmission reception TxD6 RxD6 Note Can be set as port function Remark don t care POWER6 Bit 7 of asynchronous serial interface operation mode register 6 ASIM6 TXE6 Bit 6 of ASIM6 RXE6 Bit 5 of ASIM6 PM1 Port mode regi...

Page 307: ...ssion reception Start bit Parity bit D7 D6 D5 D4 D3 1 data frame Character bits D2 D1 D0 Stop bit One data frame consists of the following bits Start bit 1 bit Character bits 7 or 8 bits Parity bit Even parity odd parity 0 parity or no parity Stop bit 1 or 2 bits The character bit length parity and stop bit length in one data frame are specified by asynchronous serial interface operation mode regi...

Page 308: ...p bit 1 bit Communication data 55H 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 3 Data length 8 bits MSB first Parity Even parity Stop bit 1 bit Communication data 55H TXD6 pin inverted output 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 4 Data length 7 bits LSB first Parity Odd parity Stop bit 2 bits Communication data 36H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 Parity Stop St...

Page 309: ...he number of bits that are 1 in the receive data including the parity bit is counted If it is odd a parity error occurs ii Odd parity Transmission Unlike even parity transmit data including the parity bit is controlled so that the number of bits that are 1 is odd If transmit data has an odd number of bits that are 1 0 If transmit data has an even number of bits that are 1 1 Reception The number of...

Page 310: ...rred to transmit shift register 6 TXS6 After that the data is sequentially output from TXS6 to the TXD6 pin When transmission is completed the parity and stop bits set by ASIM6 are appended and a transmission completion interrupt request INTST6 is generated Transmission is stopped until the data to be transmitted next is written to TXB6 Figure 14 15 shows the timing of the transmission completion ...

Page 311: ...porated in a LIN the continuous transmission function cannot be used Make sure that asynchronous serial interface transmission status register 6 ASIF6 is 00H before writing transmit data to transmit buffer register 6 TXB6 TXBF6 Writing to TXB6 Register 0 Writing enabled 1 Writing disabled Caution To transmit data continuously write the first transmit data first byte to the TXB6 register Be sure to...

Page 312: ...nsfer executed necessary number of times Yes Read ASIF6 TXBF6 0 No No Yes Transmission completion interrupt occurs Read ASIF6 TXSF6 0 No No No Yes Yes Yes Yes Completion of transmission processing Transfer executed necessary number of times Remark TXB6 Transmit buffer register 6 ASIF6 Asynchronous serial interface transmission status register 6 TXBF6 Bit 1 of ASIF6 transmit buffer data flag TXSF6 ...

Page 313: ...a 1 Data 2 Data 3 Data 2 Data 1 Data 3 FF FF Parity Stop Data 2 Parity Stop TXB6 TXS6 TXBF6 TXSF6 Start Start Note Note When ASIF6 is read there is a period in which TXBF6 and TXSF6 1 1 Therefore judge whether writing is enabled using only the TXBF6 bit Remark TXD6 TXD6 pin output INTST6 Interrupt request signal TXB6 Transmit buffer register 6 TXS6 Transmit shift register 6 ASIF6 Asynchronous seri...

Page 314: ... TXS6 TXBF6 TXSF6 POWER6 or TXE6 Start Remark TXD6 TXD6 pin output INTST6 Interrupt request signal TXB6 Transmit buffer register 6 TXS6 Transmit shift register 6 ASIF6 Asynchronous serial interface transmission status register 6 TXBF6 Bit 1 of ASIF6 TXSF6 Bit 0 of ASIF6 POWER6 Bit 7 of asynchronous serial interface operation mode register 6 ASIM6 TXE6 Bit 6 of asynchronous serial interface operati...

Page 315: ...top bit has been received the reception completion interrupt INTSR6 is generated and the data of RXS6 is written to receive buffer register 6 RXB6 If an overrun error OVE6 occurs however the receive data is not written to RXB6 Even if a parity error PE6 occurs while reception is in progress reception continues to the reception position of the stop bit and an error interrupt INTSR6 INTSRE6 is gener...

Page 316: ...tion Error Cause Parity error The parity specified for transmission does not match the parity of the receive data Framing error Stop bit is not detected Overrun error Reception of the next data is completed before data is read from receive buffer register 6 RXB6 The error interrupt can be separated into reception completion interrupt INTSR6 and error interrupt INTSRE6 by clearing bit 0 ISRM6 of as...

Page 317: ...xD6 pin outputs a high level when bit 7 POWER6 of asynchronous serial interface mode register 6 ASIM6 is set to 1 Transmission is enabled when bit 6 TXE6 of ASIM6 is set to 1 next time and SBF transmission operation is started when bit 5 SBTT6 of asynchronous serial interface control register 6 ASICL6 is set to 1 After transmission has been started the low levels of bits 13 to 20 set by bits 4 to ...

Page 318: ...st INTSR6 is generated as normal processing At this time the SBRF6 and SBRT6 bits are automatically cleared and SBF reception ends Detection of errors such as OVE6 PE6 and FE6 bits 0 to 2 of asynchronous serial interface reception error status register 6 ASIS6 is suppressed and error detection processing of UART communication is not performed In addition data transfer between receive shift registe...

Page 319: ...n POWER6 0 Transmission counter This counter stops operation cleared to 0 when bit 7 POWER6 or bit 6 TXE6 of asynchronous serial interface operation mode register 6 ASIM6 is 0 It starts counting when POWER6 1 and TXE6 1 The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 TXB6 If data are continuously transmitted the counter is cleared to 0 again whe...

Page 320: ...enerator BRGC6 MDL67 to MDL60 1 2 POWER6 TXE6 or RXE6 CKSR6 TPS63 to TPS60 fX fX 2 fX 22 fX 23 fX 24 fX 25 fX 26 fX 27 fX 28 fX 29 fX 210 8 bit timer event counter 50 output fXCLK6 Remark POWER6 Bit 7 of asynchronous serial interface operation mode register 6 ASIM6 TXE6 Bit 6 of ASIM6 RXE6 Bit 5 of ASIM6 CKSR6 Clock selection register 6 BRGC6 Baud rate generator control register 6 ...

Page 321: ...60 bits of CKSR6 register k Value set by MDL67 to MDL60 bits of BRGC6 register k 8 9 10 255 b Error of baud rate The baud rate error can be calculated by the following expression Error 1 100 Cautions 1 Keep the baud rate error during transmission to within the permissible error range at the reception destination 2 Make sure that the baud rate error during reception satisfies the range shown in 4 P...

Page 322: ... 11 1H 109 9610 0 11 10400 2H 120 10417 0 16 2H 101 10371 0 28 1H 101 10475 0 28 19200 1H 130 19231 0 16 1H 109 19220 0 11 0H 109 19220 0 11 31250 1H 80 31250 0 00 0H 134 31268 0 06 0H 67 31268 0 06 38400 0H 130 38462 0 16 0H 109 38440 0 11 0H 55 38090 0 80 76800 0H 65 76923 0 16 0H 55 76182 0 80 0H 27 77593 1 03 115200 0H 43 116279 0 94 0H 36 116389 1 03 0H 18 116389 1 03 153600 0H 33 151515 1 36...

Page 323: ...it Bit 0 Bit 1 Bit 7 Parity bit Minimum permissible data frame length Maximum permissible data frame length Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Latch timing Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit As shown in Figure 14 25 the latch timing of the receive data is determined by the counter set by baud rate generator control register 6 BRGC6 after the start bit has been de...

Page 324: ...aud rate error between UART6 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions as follows Table 14 5 Maximum Minimum Permissible Baud Rate Error Division Ratio k Maximum Permissible Baud Rate Error Minimum Permissible Baud Rate Error 8 3 53 3 61 20 4 26 4 31 50 4 56 4 58 100 4 66 4 67 255 4 72 4 73 Remarks 1 The permissible error of recepti...

Page 325: ...because the timing is initialized on the reception side when the start bit is detected Figure 14 26 Data Frame Length During Continuous Transmission Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FL 1 data frame FL FL FL FL FL FL FLstp Start bit of second byte Start bit Bit 0 Where the 1 bit data length is FL the stop bit length is FLstp and base clock frequency is fXCLK6 the following expression...

Page 326: ...n the power consumption For details see 15 4 1 Operation stop mode 2 3 wire serial I O mode MSB LSB first selectable This mode is used to communicate 8 bit data using three lines a serial clock line SCK1n and two serial data lines SI1n and SO1n The processing time of data communication can be shortened in the 3 wire serial I O mode because transmission and reception can be simultaneously executed ...

Page 327: ...r 1n CSIM1n Serial clock selection register 1n CSIC1n Port mode register 0 PM0 or port mode register 1 PM1 Port register 0 P0 or port register 1 P1 Remark n 0 µPD78F0132H n 0 1 µPD78F0133H 78F0134H 78F0136H 78F0138H 78F0138HD Figure 15 1 Block Diagram of Serial Interface CSI10 Internal bus SI10 P11 RXD0 INTCSI10 fX 2 fX 22 fX 23 fX 24 fX 25 fX 26 fX 27 SCK10 P10 TxD0 Transmit buffer register 10 SO...

Page 328: ...o the serial output pin SO1n SOTB1n can be written or read by an 8 bit memory manipulation instruction RESET input clears this register to 00H Cautions 1 Do not access SOTB1n when CSOT1n 1 during serial communication 2 The SSI11 pin can be used in the slave mode For details of the transmission reception operation see 15 4 2 2 Communication operation 2 Serial I O shift register 1n SIO1n This is an ...

Page 329: ... Symbol 7 6 5 4 3 2 1 0 CSIM10 CSIE10 TRMD10 0 DIR10 0 0 0 CSOT10 CSIE10 Operation control in 3 wire serial I O mode 0 Disables operation Note 2 and asynchronously resets the internal circuit Note 3 1 Enables operation TRMD10 Note 4 Transmit receive mode control 0 Note 5 Receive mode transmission disabled 1 Transmit receive mode DIR10 Note 6 First bit specification 0 MSB 1 LSB CSOT10 Communication...

Page 330: ... is used DIR11 Note 8 First bit specification 0 MSB 1 LSB CSOT11 Communication status flag 0 Communication is stopped 1 Communication is in progress Notes 1 Bit 0 is a read only bit 2 When using P02 SO11 P03 SI11 P04 SCK11 and P05 SSI11 TI001 as general purpose port pins see CHAPTER 4 PORT FUNCTIONS Caution 3 of Figure 15 6 and Table 15 2 3 Bit 0 CSOT11 of CSIM11 and serial I O shift register 11 S...

Page 331: ...ception timing Type 0 0 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 SI10 input timing 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 SI10 input timing 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 SI10 input timing 3 1 1 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 SI10 input timing 4 CKS102 CKS101 CKS100 CSI10 serial clock selection Note Mode 0 0 0 fX 2 5 MHz Master mode 0 0 1 fX 2 2 2 5 MHz Master mode 0 1 0 fX 2 3 1 25 MHz ...

Page 332: ...on frequency Figure 15 6 Format of Serial Clock Selection Register 11 CSIC11 Address FF89H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CSIC11 0 0 0 CKP11 DAP11 CKS112 CKS111 CKS110 CKP11 DAP11 Specification of data transmission reception timing Type 0 0 D7 D6 D5 D4 D3 D2 D1 D0 SCK11 SO11 SI11 input timing 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 SCK11 SO11 SI11 input timing 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 SCK11...

Page 333: ...g OSC clock is selected as the clock supplied to the CPU the clock of the Ring OSC oscillator is divided and supplied as the serial clock At this time the operation of serial interface CSI11 is not guaranteed 2 Do not write to CSIC11 while CSIE11 1 operation enabled 3 Clear CKP11 to 0 to use P02 SO11 P03 SI11 and P04 SCK11 as general purpose port pins 4 The phase type of the data clock is type 1 a...

Page 334: ...05 SSI11 TI001 as the chip select input pin set PM10 PM04 PM11 PM03 and PM05 to 1 At this time the output latches of P10 P04 P11 P03 and P05 may be 0 or 1 PM0 and PM1 can be set by a 1 bit or 8 bit memory manipulation instruction RESET input sets these registers to FFH Note µPD78F0133H 78F0134H 78F0136H 78F0138H and 78F0138HD only Figure 15 7 Format of Port Mode Register 0 PM0 7 1 6 PM06 5 PM05 4 ...

Page 335: ...ark n 0 µPD78F0132H n 0 1 µPD78F0133H 78F0134H 78F0136H 78F0138H 78F0138HD Serial operation mode register 10 CSIM10 Address FF80H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CSIM10 CSIE10 TRMD10 0 DIR10 0 0 0 CSOT10 CSIE10 Operation control in 3 wire serial I O mode 0 Disables operation Note 1 and asynchronously resets the internal circuit Note 2 Notes 1 When using P10 SCK10 TxD0 P11 SI10 RxD0 and ...

Page 336: ... port register 1 P1 The basic procedure of setting an operation in the 3 wire serial I O mode is as follows 1 Set the CSIC1n register see Figures 15 5 and 15 6 2 Set bits 0 and 4 to 6 CSOT1n DIR1n SSE11 serial interface CSI11 only and TRMD1n of the CSIM1n register see Figures 15 3 and 15 4 3 Set bit 7 CSIE1n of the CSIM1n register to 1 Transmission reception is enabled 4 Write data to transmit buf...

Page 337: ...transmission Note 3 RxD0 P11 SO10 SCK10 input Note 3 1 1 1 0 0 1 Slave transmission reception Note 3 SI10 SO10 SCK10 input Note 3 1 0 1 Note 1 Note 1 0 1 Master reception SI10 P12 SCK10 output 1 1 Note 1 Note 1 0 0 0 1 Master transmission RxD0 P11 SO10 SCK10 output 1 1 1 0 0 0 1 Master transmission reception SI10 SO10 SCK10 output Notes 1 Can be set as port function 2 To use P10 SCK10 TxD0 as port...

Page 338: ...ion Note 3 P03 SO11 SCK11 input Note 3 SSI11 0 Note 1 Note 1 TI001 P05 1 1 1 1 0 0 1 1 Slave transmission reception Note 3 SI11 SO11 SCK11 input Note 3 SSI11 1 0 0 1 Note 1 Note 1 0 1 Note 1 Note 1 Master reception SI11 P02 SCK11 output TI001 P05 1 1 0 Note 1 Note 1 0 0 0 1 Note 1 Note 1 Master transmission P03 SO11 SCK11 output TI001 P05 1 1 0 1 0 0 0 1 Note 1 Note 1 Master transmission reception...

Page 339: ...SSI11 pin Transmission reception or reception is held therefore even if SOTB11 is written or SIO11 is read transmission reception or reception will not be started 3 Data is written to SOTB11 or data is read from SIO11 while a high level is input to the SSI11 pin then a low level is input to the SSI11 pin Transmission reception or reception is started 4 A high level is input to the SSI11 pin during...

Page 340: ...1n 0 DAP1n 0 SSE11 1Note AAH ABH 56H ADH 5AH B5H 6AH D5H 55H communication data 55H is written to SOTB1n SCK1n SOTB1n SIO1n CSOT1n CSIIF1n SO1n SI1n receive AAH Read write trigger INTCSI1n SSI11Note Note The SSE11 flag and SSI11 pin are available only for serial interface CSI11 and are used in the slave mode Remark n 0 µPD78F0132H n 0 1 µPD78F0133H 78F0134H 78F0136H 78F0138H 78F0138HD ...

Page 341: ...P1n 0 DAP1n 1 SSE11 1Note ABH 56H ADH 5AH B5H 6AH D5H SCK1n SOTB1n SIO1n CSOT1n CSIIF1n SO1n SI1n input AAH AAH 55H communication data 55H is written to SOTB1n Read write trigger INTCSI1n SSI11Note Note The SSE11 flag and SSI11 pin are available only for serial interface CSI11 and are used in the slave mode Remark n 0 µPD78F0132H n 0 1 µPD78F0133H 78F0134H 78F0136H 78F0138H 78F0138HD ...

Page 342: ...2 CKP1n 0 DAP1n 1 D7 D6 D5 D4 D3 D2 D1 D0 SCK1n SO1n Writing to SOTB1n or reading from SIO1n SI1n capture CSIIF1n CSOT1n c Type 3 CKP1n 1 DAP1n 0 D7 D6 D5 D4 D3 D2 D1 D0 SCK1n SO1n Writing to SOTB1n or reading from SIO1n SI1n capture CSIIF1n CSOT1n d Type 4 CKP1n 1 DAP1n 1 D7 D6 D5 D4 D3 D2 D1 D0 SCK1n SO1n Writing to SOTB1n or reading from SIO1n SI1n capture CSIIF1n CSOT1n Remark n 0 µPD78F0132H ...

Page 343: ...e SIO1n register via the SI1n pin The second and subsequent bits are latched by the SIO1n register to the output latch at the next falling or rising edge of SCK1n and the data is output from the SO1n pin 2 When CKP1n 0 DAP1n 1 or CKP1n 1 DAP1n 1 SCK1n SOTB1n SIO1n SO1n Writing to SOTB1n or reading from SIO1n First bit 2nd bit 3rd bit Output latch The first bit is directly latched by the SOTB1n reg...

Page 344: ...alue of SO1n Pin Last Bit 1 Type 1 when CKP1n 0 and DAP1n 0 or CKP1n 1 DAP1n 0 SCK1n SOTB1n SIO1n SO1n Writing to SOTB1n or reading from SIO1n Next request is issued Last bit Output latch 2 Type 2 when CKP1n 0 and DAP1n 1 or CKP1n 1 DAP1n 1 SCK1n SOTB1n SIO1n SO1n Last bit Writing to SOTB1n or reading from SIO1n Next request is issued Output latch Remark n 0 µPD78F0132H n 0 1 µPD78F0133H 78F0134H ...

Page 345: ...0 Note Outputs low level Note 2 DAP1n 0 Value of SO1n latch low level output DIR1n 0 Value of bit 7 of SOTB1n TRMD1n 1 DAP1n 1 DIR1n 1 Value of bit 0 of SOTB1n Notes 1 The actual output of the SO10 P12 or SO11 P02 pin is determined according to PM12 and P12 or PM02 and P02 as well as the SO1n output 2 Status after reset Caution If a value is written to TRMD1n DAP1n and DIR1n the output value of SO...

Page 346: ...vision 16 2 Configuration of Multiplier Divider The multiplier divider includes the following hardware Table 16 1 Configuration of Multiplier Divider Item Configuration Registers Remainder data register 0 SDR0 Multiplication division data registers A0 MDA0H MDA0L Multiplication division data registers B0 MDB0 Control register Multiplier divider control register 0 DMUC0 Figure 16 1 shows the block ...

Page 347: ...lock Start Clear 17 bit adder Controller Multiplication division data register B0 MDB0 MDB0H MDB0L Remainder data register 0 SDR0 SDR0H SDR0L 6 bit counter DMUSEL0 Multiplier divider control register 0 DMUC0 Controller Multiplication division data register A0 MDA0H MDA0HH MDA0HL MDA0L MDA0LH MDA0LL Controller DMUE MDA000 INTDMU ...

Page 348: ...a 32 bit register that sets a 16 bit multiplier A in the multiplication mode and a 32 bit dividend in the division mode and stores the 32 bit result of the operation higher 16 bits MDA0H lower 16 bits MDA0L Figure 16 3 Format of Multiplication Division Data Register A0 MDA0H MDA0L Address FF62H FF63H FF64H FF65H After reset 0000H 0000H R W Symbol FF65H MDA0HH FF64H MDA0HL MDA0H MDA 031 MDA 030 MDA...

Page 349: ... of multiplier divider control register 0 DMUC0 is set to 1 MDA0H and MDA0L can be set by an 8 bit or 16 bit memory manipulation instruction RESET input clears this register to 0000H 3 Multiplication division data register B0 MDB0 MDB0 is a register that stores a 16 bit multiplier B in the multiplication mode and a 16 bit divisor in the division mode This register can be set by an 8 bit or 16 bit ...

Page 350: ...0 6 7 5 Note When DMUE is set to 1 the operation is started DMUE is automatically cleared to 0 after the operation is complete Cautions 1 If DMUE is cleared to 0 during operation processing when DMUE is 1 the operation result is not guaranteed If the operation is completed while the clearing instruction is being executed the operation result is guaranteed provided that the interrupt flag is set 2 ...

Page 351: ...eted when 16 internal clocks have been issued after the start of the operation intermediate data is stored in the MDA0L and MDA0H registers during operation and therefore the read values of these registers are not guaranteed End of operation 4 The operation result data is stored in the MDA0L and MDA0H registers 5 DMUE is cleared to 0 end of operation 6 After the operation an interrupt request sign...

Page 352: ... 4 5 6 7 8 9 A B C D E F 10 0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 006D 0000 00DA XXXX 00DA XXXX XXXX XXXX 0049 8036 0024 C01B 005B E00D 0077 7006 003B B803 0067 5C01 007D 2E00 003E 9700 001F 4B80 000F A5C0 0007 D2E0 0003 E970 0001 F4B8 0000 FA5C 0000 7D2E 0093 XXXX Internal clock DMUE DMUSEL0 Counter INTDMU ...

Page 353: ...locks have been issued after the start of the operation intermediate data is stored in the MDA0L and MDA0H registers and remainder data register 0 SDR0 during operation and therefore the read values of these registers are not guaranteed End of operation 4 The result data is stored in the MDA0L MDA0H and SDR0 registers 5 DMUE is cleared to 0 end of operation 6 After the operation an interrupt reque...

Page 354: ... 4 5 6 7 8 19 1A 1B 1C 1D 1E 1F 20 0 0 0000 0001 0003 0006 000D 0003 0007 000E 0004 000B 0016 0014 0010 0008 0011 000B 0016 B974 4B0C DCBA 2586 XXXX XXXX XXXX 72E8 A618 E5D1 2C30 CBA2 6860 A744 BAC1 2E89 6182 6D12 C304 BA25 8609 0C12 64D8 1824 C9B0 3049 9361 6093 26C3 C126 4D87 824C 9B0E 0499 361D 0932 6C3A 0018 XXXX Internal clock DMUE DMUSEL0 Counter INTDMU 0 ...

Page 355: ...more interrupts with the same priority are generated simultaneously each interrupt is serviced according to its predetermined priority see Table 17 1 A standby release signal is generated and STOP and HALT modes are released Nine external interrupt requests and 19 16 in the µPD78F0132H internal interrupt requests are provided as maskable interrupts 2 Software interrupt This is a vectored interrupt...

Page 356: ...ecified 001EH 14 INTTM000 Match between TM00 and CR000 when compare register is specified TI010 pin valid edge detection when capture register is specified 0020H 15 INTTM010 Match between TM00 and CR010 when compare register is specified TI000 pin valid edge detection when capture register is specified 0022H 16 INTAD End of A D conversion 0024H 17 INTSR0 End of UART0 reception or reception error g...

Page 357: ...e register is specified TI001 pin valid edge detection when capture register is specified Internal 003AH A Software BRK BRK instruction execution 003EH D RESET Reset input POC Power on clear LVI Low voltage detection Note 4 Clock monitor High speed system clock oscillation stop detection Reset WDT WDT overflow 0000H Notes 1 The default priority is the priority applicable when two or more maskable ...

Page 358: ...r Vector table address generator Standby release signal B External maskable interrupt INTP0 to INTP7 Internal bus Interrupt request IF MK IE PR ISP Priority controller Vector table address generator Standby release signal External interrupt edge enable register EGP EGN Edge detector IF Interrupt request flag IE Interrupt enable flag ISP In service priority flag MK Interrupt mask flag PR Priority s...

Page 359: ...flag ISP In service priority flag MK Interrupt mask flag PR Priority specification flag KRM Key return mode register 17 3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions Interrupt request flag register IF0L IF0H IF1L IF1H Interrupt mask flag register MK0L MK0H MK1L MK1H Priority specification flag register PR0L PR0H PR1L PR1H...

Page 360: ...1 TMIFH1 TMMKH1 TMPRH1 INTTMH0 TMIFH0 TMMKH0 TMPRH0 INTTM50 TMIF50 TMMK50 TMPR50 INTTM000 TMIF000 TMMK000 TMPR000 INTTM010 TMIF010 TMMK010 TMPR010 INTAD ADIF IF1L ADMK MK1L ADPR PR1L INTSR0 SRIF0 SRMK0 SRPR0 INTWTI WTIIF WTIMK WTIPR INTTM51 TMIF51 TMMK51 TMPR51 INTKR KRIF KRMK KRPR INTWT WTIF WTMK WTPR INTP6 PIF6 PMK6 PPR6 INTP7 PIF7 PMK7 PPR7 INTDMU DMUIF IF1H DMUMK MK1H DMUPR PR1H INTCSI11 Note ...

Page 361: ...of Interrupt Request Flag Registers IF0L IF0H IF1L IF1H Address FFE0H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF0L SREIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 LVIIF Address FFE1H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF0H TMIF010 TMIF000 TMIF50 TMIFH0 TMIFH1 DUALIF0 STIF6 SRIF6 Address FFE2H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF1L PIF7 PIF6 WTIF KRIF TMIF51 WTIIF SRIF0 ADIF Address FFE3H ...

Page 362: ...n must be 1 bit memory manipulation instructions CLR1 If an 8 bit memory manipulation instruction IF0L 0xfe is described in C language for example it is converted to the following three assembly instructions after compilation mov a IF0L and a 0FEH mov IF0L a In this case at the timing between mov a IF0L and mov IF0L a if the request flag of another bit of the identical interrupt request flag regis...

Page 363: ...s MK0L MK0H MK1L MK1H Address FFE4H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK0L SREMK6 PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMK Address FFE5H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK0H TMMK010 TMMK000 TMMK50 TMMKH0 TMMKH1 DUALMK0 STMK6 SRMK6 Address FFE6H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK1L PMK7 PMK6 WTMK KRMK TMMK51 WTIMK SRMK0 ADMK Address FFE7H After reset DFH R W Symbol 7 6 5 4...

Page 364: ...ty Specification Flag Registers PR0L PR0H PR1L PR1H Address FFE8H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR0L SREPR6 PPR5 PPR4 PPR3 PPR2 PPR1 PPR0 LVIPR Address FFE9H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR0H TMPR010 TMPR000 TMPR50 TMPRH0 TMPRH1 DUALPR0 STPR6 SRPR6 Address FFEAH After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR1L PPR7 PPR6 WTPR KRPR TMPR51 WTIPR SRPR0 ADPR Address FFEBH Afte...

Page 365: ...EGP0 Address FF49H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 EGN EGN7 EGN6 EGN5 EGN4 EGN3 EGN2 EGN1 EGN0 EGPn EGNn INTPn pin valid edge selection n 0 to 7 0 0 Edge detection disabled 0 1 Falling edge 1 0 Rising edge 1 1 Both rising and falling edges Table 17 3 shows the ports corresponding to EGPn and EGNn Table 17 3 Ports Corresponding to EGPn and EGNn Detection Enable Register Edge Detection Po...

Page 366: ...ed into a stack and the IE flag is reset to 0 If a maskable interrupt request is acknowledged the contents of the priority specification flag of the acknowledged interrupt are transferred to the ISP flag The PSW contents are also saved into the stack with the PUSH PSW instruction They are restored from the stack with the RETI RETB and POP PSW instructions RESET input sets PSW to 02H Figure 17 6 Fo...

Page 367: ...0 7 clocks 32 clocks When PR 1 8 clocks 33 clocks Note If an interrupt request is generated just before a divide instruction the wait time becomes longer Remark 1 clock 1 fCPU fCPU CPU clock If two or more maskable interrupt requests are generated simultaneously the request with a higher priority level specified in the priority specification flag is acknowledged first If two or more interrupts req...

Page 368: ...eld pending Interrupt request held pending Interrupt request held pending Interrupt request held pending Interrupt request held pending Vectored interrupt servicing Any high priority interrupt request among those simultaneously generated Any high priority interrupt request among those simultaneously generated with PR 0 IF Interrupt request flag MK Interrupt mask flag PR Priority specification flag...

Page 369: ...servicing program CPU processing IF PR 1 IF PR 0 6 clocks 25 clocks Remark 1 clock 1 fCPU fCPU CPU clock 17 4 2 Software interrupt request acknowledgement A software interrupt acknowledge is acknowledged by BRK instruction execution Software interrupts cannot be disabled If a software interrupt request is acknowledged the contents are saved into the stacks in the order of the program status word P...

Page 370: ...ently being serviced is generated during interrupt servicing it is not acknowledged for multiple interrupt servicing Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower priority are held pending When servicing of the current interrupt ends the pending interrupt request is acknowledged following execution of at least one main p...

Page 371: ...dged the EI instruction must always be issued to enable interrupt request acknowledgment Example 2 Multiple interrupt servicing does not occur due to priority control Main processing INTxx servicing INTyy servicing INTxx PR 0 INTyy PR 1 EI RETI IE 0 IE 0 EI 1 instruction execution RETI IE 1 IE 1 Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its prio...

Page 372: ...nstruction execution RETI RETI INTxx PR 0 INTyy PR 0 IE 0 IE 0 IE 1 IE 1 Interrupts are not enabled during servicing of interrupt INTxx EI instruction is not issued therefore interrupt request INTyy is not acknowledged and multiple interrupt servicing does not take place The INTyy interrupt request is held pending and is acknowledged following execution of one main processing instruction PR 0 High...

Page 373: ...1L IF1H MK0L MK0H MK1L MK1H PR0L PR0H PR1L and PR1H registers Caution The BRK instruction is not one of the above listed interrupt request hold instructions However the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared Therefore even if a maskable interrupt request is generated during execution of the BRK instruction the interrupt request is not acknowl...

Page 374: ... bit units KRM2 Controls KR2 signal in 1 bit units KRM3 Controls KR3 signal in 1 bit units KRM4 Controls KR4 signal in 1 bit units KRM5 Controls KR5 signal in 1 bit units KRM6 Controls KR6 signal in 1 bit units KRM7 Controls KR7 signal in 1 bit units 18 2 Configuration of Key Interrupt The key interrupt includes the following hardware Table 18 2 Configuration of Key Interrupt Item Configuration Co...

Page 375: ...ot detect key interrupt signal Detects key interrupt signal KRMn 0 1 Key interrupt mode control KRM KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 Address FF6EH After reset 00H R W Symbol 7 6 5 4 3 2 0 Cautions 1 If any of the KRM0 to KRM7 bits used is set to 1 set bits 0 to 7 PU70 to PU77 of the corresponding pull up resistor register 7 PU7 to 1 2 If KRM is changed the interrupt request flag may be set There...

Page 376: ...ion execution 4 Operates using the CPU clock at HALT instruction execution Caution The RSTOP setting is valid only when Can be stopped by software is set for Ring OSC by the option byte Remark MSTOP Bit 7 of the main OSC control register MOC MCC Bit 7 of the processor clock control register PCC RSTOP Bit 0 of the Ring OSC mode register RCM MCM0 Bit 0 of the main clock mode register MCM The standby...

Page 377: ...n be used only when CPU is operating on the high speed system clock or Ring OSC clock HALT mode can be used when CPU is operating on the high speed system clock Ring OSC clock or subsystem clock However when the STOP instruction is executed during Ring OSC clock operation the high speed system clock oscillator stops but Ring OSC oscillator does not stop 2 When shifting to the STOP mode be sure to ...

Page 378: ...ST14 MOST15 MOST16 MOST11 MOST13 MOST14 MOST15 MOST16 Oscillation stabilization time status fXP 10 MHz fXP 16 MHz 1 0 0 0 0 2 11 fXP min 204 8 µs min 128 µs min 1 1 0 0 0 2 13 fXP min 819 2 µs min 512 µs min 1 1 1 0 0 2 14 fXP min 1 64 ms min 1 02 ms min 1 1 1 1 0 2 15 fXP min 3 27 ms min 2 04 ms min 1 1 1 1 1 2 16 fXP min 6 55 ms min 4 09 ms min Cautions 1 After the above time has elapsed the bit...

Page 379: ... 3 27 ms 2 04 ms 1 0 1 2 16 fXP 6 55 ms 4 09 ms Other than above Setting prohibited Cautions 1 To set the STOP mode when the high speed system clock is used as the CPU clock set OSTS before executing a STOP instruction 2 Before setting OSTS confirm with OSTC that the desired oscillation stabilization time has elapsed 3 If the STOP mode is entered and then released while the Ring OSC clock is being...

Page 380: ... not guaranteed when count clock other than TI51 is selected 8 bit timer H0 Operable Operation not guaranteed when count clock other than TM50 output is selected during 8 bit timer event counter 50 operation 8 bit timer H1 Operable Operation not guaranteed when count clock other than fR 27 is selected Watch timer Operable OperableNote 3 Operable OperableNote 3 OperableNote 4 Operation not guarante...

Page 381: ... operation 8 bit timer H1 Operable Operable only when the high speed system clock is selected as the count clock Operable only when fR 27 is selected as the count clock Operation stopped Watch timer Operable Operable only when subsystem clock is selected Ring OSC cannot be stoppedNote 3 Operable Operable Watchdog timer Ring OSC can be stoppedNote 3 Operation stopped A D converter Operable Not oper...

Page 382: ... the next address instruction is executed Figure 19 3 HALT Mode Release by Interrupt Request Generation HALT instruction Wait Wait Operating mode HALT mode Operating mode Oscillation High speed system clock Ring OSC clock or subsystem clock Status of CPU Standby release signal Interrupt request Remarks 1 The broken lines indicate the case when the interrupt request which has released the standby m...

Page 383: ...h speed system clock Operating mode HALT mode Reset period Operation stopped Operating mode Oscillates Oscillation stopped Oscillates Status of CPU High speed system clock Oscillation stabilization time 211 fXP to 216 fXP Ring OSC clock 17 fR 2 When Ring OSC clock is used as CPU clock HALT instruction RESET signal Ring OSC clock Operating mode HALT mode Reset period Operation stopped Operating mod...

Page 384: ...mode Oscillates Status of CPU Ring OSC clock 17 fR Subsystem clock Remark fR Ring OSC clock oscillation frequency Table 19 3 Operation in Response to Interrupt Request in HALT Mode Release Source MK PR IE ISP Operation 0 0 0 Next address instruction execution 0 0 1 Interrupt servicing execution 0 1 0 1 0 1 0 Next address instruction execution 0 1 1 1 Interrupt servicing execution Maskable interrup...

Page 385: ...atch Status before STOP mode was set is retained 16 bit timer event counter 00 Operation stopped 16 bit timer event counter 01Note 2 Operation stopped 8 bit timer event counter 50 Operable only when TI50 is selected as the count clock 8 bit timer event counter 51 Operable only when TI51 is selected as the count clock 8 bit timer H0 Operable only when TM50 output is selected as the count clock duri...

Page 386: ...tion is executed Ring OSC clock High speed system clock High speed system clock is selected as CPU clock when STOP instruction is executed STOP mode release STOP mode Operation stopped 17 fR Clock switched by software Ring OSC clock High speed system clock HALT status oscillation stabilization time set by OSTS High speed system clock The STOP mode can be released by the following two sources ...

Page 387: ...lock Operating mode Operating mode Oscillates Oscillates STOP instruction STOP mode Wait set by OSTS Standby release signal Oscillation stabilization wait HALT mode status Oscillation stopped High speed system clock Status of CPU Oscillation stabilization time set by OSTS High speed system clock High speed system clock 2 When Ring OSC clock is used as CPU clock Operating mode Operating mode Oscill...

Page 388: ...1 fXP to 216 fXP Ring OSC clock 17 fR Oscillation stopped 2 When Ring OSC clock is used as CPU clock STOP instruction RESET signal Ring OSC clock Operating mode STOP mode Reset period Operation stopped Operating mode Oscillates Oscillation stopped Oscillates Status of CPU Ring OSC clock 17 fR Ring OSC clock Remarks 1 fXP High speed system clock oscillation frequency 2 fR Ring OSC clock oscillation...

Page 389: ... input or during the oscillation stabilization time just after reset release except for P130 which is low level output When a high level is input to the RESET pin the reset is released and program execution starts using the Ring OSC clock after the CPU clock operation has stopped for 17 fR s A reset generated by the watchdog timer and clock monitor sources is automatically released after the reset...

Page 390: ... Set Set Clear Clear Set Reset signal Reset signal to LVIM LVIS register Watchdog timer reset signal Clock monitor reset signal RESET Power on clear circuit reset signal Low voltage detector reset signal Caution An LVI circuit internal reset does not reset the LVI circuit Remarks 1 LVIM Low voltage detection register 2 LVIS Low voltage detection level selection register ...

Page 391: ...set is effected the output signal of P130 can be dummy output as the CPU reset signal Figure 20 3 Timing of Reset Due to Watchdog Timer Overflow Hi Z Normal operation Reset period Oscillation stop CPU clock Watchdog timer overflow Internal reset signal Port pin except P130 Operation stop 17 fR Normal operation Reset processing Ring OSC clock High speed system clock Ring OSC clock Note Port pin P13...

Page 392: ...top 17 fR Normal operation Reset processing Ring OSC clock High speed system clock Ring OSC clock Port pin P130 Note Note Set P130 to high level output by software Remarks 1 When reset is effected P130 outputs a low level If P130 is set to output a high level before reset is effected the output signal of P130 can be dummy output as the CPU reset signal 2 For the reset timing of the power on clear ...

Page 393: ... 00H Timer counters 00 01 TM00 TM01 0000H Capture compare registers 000 010 001 011 CR000 CR010 CR001 CR011 0000H Mode control registers 00 01 TMC00 TMC01 00H Prescaler mode registers 00 01 PRM00 PRM01 00H Capture compare control registers 00 01 CRC00 CRC01 00H 16 bit timer event counters 00 01 Note 3 Timer output control registers 00 01 TOC00 TOC01 00H Timer counters 50 51 TM50 TM51 00H Compare r...

Page 394: ... interface operation mode register 6 ASIM6 01H Asynchronous serial interface reception error status register 6 ASIS6 00H Asynchronous serial interface transmission status register 6 ASIF6 00H Clock selection register 6 CKSR6 00H Baud rate generator control register 6 BRGC6 FFH Serial interface UART6 Asynchronous serial interface control register 6 ASICL6 16H Transmit buffer registers 10 11 SOTB10 ...

Page 395: ...flag register 1H MK1H DFH Priority specification flag registers 0L 0H 1L 1H PR0L PR0H PR1L PR1H FFH External interrupt rising edge enable register EGP 00H Interrupt External interrupt falling edge enable register EGN 00H Flash protect command register PFCMD Undefined Flash status register PFS 00H Flash memory Flash programming mode control register FLPMC 0XH Note 2 Notes 1 These values vary depend...

Page 396: ...eset request is not generated or RESF is cleared 1 Internal reset request is generated CLMRF Internal reset request by clock monitor CLM 0 Internal reset request is not generated or RESF is cleared 1 Internal reset request is generated LVIRF Internal reset request by low voltage detector LVI 0 Internal reset request is not generated or RESF is cleared 1 Internal reset request is generated Note The...

Page 397: ...llation stabilization time When the Ring OSC clock is stopped Remark MSTOP Bit 7 of the main OSC control register MOC MCC Bit 7 of the processor clock control register PCC 21 2 Configuration of Clock Monitor The clock monitor includes the following hardware Table 21 1 Configuration of Clock Monitor Item Configuration Control register Clock monitor mode register CLM Figure 21 1 Block Diagram of Clo...

Page 398: ...T input clears this register to 00H Figure 21 2 Format of Clock Monitor Mode Register CLM 7 0 CLME 0 1 Symbol CLM Address FFA9H After reset 00H R W 6 0 Disables clock monitor operation Enables clock monitor operation 5 0 4 0 3 0 Enables disables clock monitor operation 2 0 1 0 0 CLME Cautions 1 Once bit 0 CLME is set to 1 it cannot be cleared to 0 except by RESET input or the internal reset signal...

Page 399: ...he main OSC control register MOC MCC Bit 7 of the processor clock control register PCC Table 21 2 Operation Status of Clock Monitor When CLME 1 CPU Operation Clock Operation Mode High Speed System Clock Status Ring OSC Clock Status Clock Monitor Status Oscillating STOP mode Stopped Stopped Note Oscillating RESET input Stopped Note Stopped Oscillating Operating High speed system clock Normal operat...

Page 400: ... stopped Oscillation stabilization time Normal operation Clock supply stopped Normal operation Ring OSC clock Monitoring Monitoring stopped Monitoring Waiting for end of oscillation stabilization time Oscillation stopped 17 clocks Set to 1 by software RESET RESET input clears bit 0 CLME of the clock monitor mode register CLM to 0 and stops the clock monitor operation Even if CLME is set to 1 by so...

Page 401: ...are at the end of the oscillation stabilization time reset value of OSTS register is 05H 216 fXP of the high speed system clock monitoring is started 4 Clock monitor status after STOP mode is released CLME 1 is set when CPU clock operates on high speed system clock and before entering STOP mode Clock monitor status Monitoring Monitoring stopped Monitoring CLME Ring OSC clock High speed system cloc...

Page 402: ...d system clock oscillation is stopped by software Clock monitor status CLME MSTOP or MCCNote Ring OSC clock High speed system clock Oscillation stabilization time time set by OSTS register Normal operation Ring OSC clock or subsystem clockNote Monitoring Monitoring stopped Monitoring CPU operation Monitoring stopped Oscillation stopped When bit 0 CLME of the clock monitor mode register CLM is set ...

Page 403: ...itoring Monitoring stopped Monitoring CLME When bit 0 CLME of the clock monitor mode register CLM is set to 1 before or while oscillation of the Ring OSC clock is stopped monitoring automatically starts after the Ring OSC clock is stopped Monitoring is stopped when oscillation of the Ring OSC clock is stopped Note If it is specified by the option byte that Ring OSC cannot be stopped the setting of...

Page 404: ...5 5 V when the Ring OSC clock or subsystem clock is used but be sure to use the product in a voltage range of 2 2 to 5 5 V because the detection voltage VPOC of the POC circuit is 2 1 V 0 1 V Remark This product incorporates multiple hardware functions that generate an internal reset signal A flag that indicates the reset cause is located in the reset control flag register RESF for when an interna...

Page 405: ...r on Clear Circuit Reference voltage source Internal reset signal VDD VDD 22 3 Operation of Power on Clear Circuit In the power on clear circuit the supply voltage VDD and detection voltage VPOC are compared and when VDD VPOC an internal reset signal is generated Figure 22 2 Timing of Internal Reset Signal Generation in Power on Clear Circuit Time Supply voltage VDD POC detection voltage VPOC Inte...

Page 406: ...s 50 ms or less in vicinity of POC detection voltage Yes Power on clear The Ring OSC clock is set as the CPU clock when the reset signal is generated The cause of reset power on clear WDT LVI or clock monitor can be identified by the RESF register Change the CPU clock from the Ring OSC clock to the high speed system clock Check the stabilization of oscillation of the high speed system clock by usi...

Page 407: ...After Release of Reset 2 2 Checking reset cause Yes No Check reset cause Power on clear external reset generated Reset processing by watchdog timer Reset processing by clock monitor Reset processing by low voltage detector No No WDTRF of RESF register 1 CLMRF of RESF register 1 LVIRF of RESF register 1 Yes Yes ...

Page 408: ...ware Operable in STOP mode When the low voltage detector is used to reset bit 0 LVIRF of the reset control flag register RESF is set to 1 if reset occurs For details of RESF refer to CHAPTER 20 RESET FUNCTION 23 2 Configuration of Low Voltage Detector The block diagram of the low voltage detector is shown below Figure 23 1 Block Diagram of Low Voltage Detector LVIS1 LVIS0 LVION Reference voltage s...

Page 409: ...pt signal when supply voltage VDD detection voltage VLVI 1 Generates internal reset signal when supply voltage VDD detection voltage VLVI LVIF Note 5 Low voltage detection flag 0 Supply voltage VDD detection voltage VLVI or when operation is disabled 1 Supply voltage VDD detection voltage VLVI Notes 1 Bit 0 is read only 2 Bit 4 may be 0 or 1 This bit corresponds to the LVIE bit in the 78K0 KE1 3 L...

Page 410: ... LVIS3 4 0 5 0 6 0 7 0 Symbol LVIS Address FFBFH After reset 00H R W LVIS3 LVIS2 LVIS1 LVIS0 Detection level Note 0 0 0 0 VLVI0 4 3 V 0 2 V 0 0 0 1 VLVI1 4 1 V 0 2 V 0 0 1 0 VLVI2 3 9 V 0 2 V 0 0 1 1 VLVI3 3 7 V 0 2 V 0 1 0 0 VLVI4 3 5 V 0 2 V 0 1 0 1 VLVI5 3 3 V 0 15 V 0 1 1 0 VLVI6 3 1 V 0 15 V 0 1 1 1 VLVI7 2 85 V 0 15 V 1 0 0 0 VLVI8 2 6 V 0 1 V 1 0 0 1 VLVI9 2 35 V 0 1 V Other than above Sett...

Page 411: ...M to 1 enables LVI operation 4 Use software to instigate a wait of at least 0 2 ms 5 Confirm that supply voltage VDD detection voltage VLVI with bit 0 LVIF of LVIM 6 Set bit 1 LVIMD of LVIM to 1 generates internal reset signal when supply voltage VDD detection voltage VLVI Figure 23 4 shows the timing of the internal reset signal generated by the low voltage detector The numbers in this timing cha...

Page 412: ...reset signal Cleared by software Not cleared Not cleared Not cleared Not cleared Cleared by software 5 6 Clear Clear Clear 4 0 2 ms or longer LVION flag set by software LVIMD flag set by software H 1 Note 1 3 Notes 1 The LVIMK flag is set to 1 by RESET input 2 The LVIF flag may be set 1 3 LVIRF is bit 0 of the reset control flag register RESF For details of RESF see CHAPTER 20 RESET FUNCTION Remar...

Page 413: ...upply voltage VDD detection voltage VLVI with bit 0 LVIF of LVIM 6 Clear the interrupt request flag of LVI LVIIF to 0 7 Release the interrupt mask flag of LVI LVIMK 8 Execute the EI instruction when vector interrupts are used Figure 23 5 shows the timing of the internal reset signal generated by the low voltage detector The numbers in this timing chart correspond to 1 to 7 above When stopping oper...

Page 414: ... Cleared by software LVIMK flag set by software LVIF flag INTLVI LVIIF flag Internal reset signal 3 5 6 Cleared by software 4 0 2 ms or longer LVION flag set by software Note 2 Note 2 1 Note 1 Notes 1 The LVIMK flag is set to 1 by RESET input 2 The LVIF and LVIIF flags may be set 1 Remark 1 to 7 in Figure 23 5 above correspond to 1 to 7 in the description of when starting operation in 23 4 2 When ...

Page 415: ...ay be repeatedly reset and released from the reset status In this case the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action a below 2 When used as interrupt Interrupt requests may be frequently generated Take action b below In this system take the following actions Action a When used as reset After releasing the reset signal wa...

Page 416: ...ck to the high speed system clock Check the stabilization of oscillation of the high speed system clock by using the OSTC register TMIFH1 1 Interrupt request is generated Initialization of ports 8 bit timer H1 can operate with the Ring OSC clock Source fR 480 kHz MAX 27 compare value 200 53 ms fR Ring OSC clock oscillation frequency No Note 1 Reset Checking cause of resetNote 2 Check stabilization...

Page 417: ...egister 1 LVIRF of RESF register 1 Yes No b When used as interrupt Check that supply voltage VDD detection voltage VLVI in the servicing routine of the LVI interrupt by using bit 0 LVIF of the low voltage detection register LVIM Clear bit 0 LVIIF of interrupt request flag register 0L IF0L to 0 and enable interrupts EI In a system where the supply voltage fluctuation period is long in the vicinity ...

Page 418: ...ash memory 0 0 0 0 RINGOSC 0000H 0080H 0 Figure 24 2 Format of Option Byte Address 0080H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RINGOSC RINGOSC Ring OSC oscillation 0 Can be stopped by software 1 Cannot be stopped Cautions 1 To use the boot swap function be sure to store the option data in the boot cluster 1 for the boot swap function see 26 9 Boot Swap Function 2 Be sure to clear bits 1 to 7 to 0 Remark A...

Page 419: ... ROM correction cannot be emulated by the in circuit emulator 25 2 Configuration of ROM Correction The ROM correction includes the following hardware Table 25 1 Configuration of ROM Correction Item Configuration Registers Correction address registers 0 and 1 CORAD0 CORAD1 Control register Correction control register CORCN Figure 25 1 shows a block diagram of the ROM correction Figure 25 1 Block Di...

Page 420: ...F39H After reset 0000H R W R W CORAD1 R W Cautions 1 Set the CORAD0 and CORAD1 when bit 1 COREN0 and bit 3 COREN1 of the correction control register CORCN see Figure 25 3 are 0 2 Only addresses where operation codes are stored can be set in CORAD0 and CORAD1 3 Do not set the following addresses to CORAD0 and CORAD1 Address value in table area of table reference instruction CALLT instruction 0040H ...

Page 421: ...ection signal and correction status flags show the values are matched CORCN is set by a 1 bit or 8 bit memory manipulation instruction RESET input clears CORCN to 00H Clear CORST0 and CORST1 using software Figure 25 3 Format of Correction Control Register 7 0 6 0 5 0 4 0 COREN1 CORST1 COREN0 CORST0 Symbol CORCN Address FF8AH After reset COREN0 0 1 CORST0 0 1 COREN1 0 1 CORST1 0 1 R W R WNote 00H C...

Page 422: ...art 1000H 1002H Internal flash memory Internal expansion RAM F400H F702H F7FDH F7FFH 1 2 3 EFFFH 1 Branches to address F7FDH when the preset value 1000H in the correction address register matches the fetch address value after the main program is started 2 Branches to any address address F702H in this example by setting the entire space branch instruction BR addr16 to address F7FDH with the main pr...

Page 423: ...MTM outside the microcontroller When two places should be corrected store the branch destination judgment program as well The branch destination judgment program checks which one of the addresses set to correction address registers 0 and 1 CORAD0 or CORAD1 generates the correction branch Figure 25 5 Example of Storing to EEPROM When One Place Is Corrected RA78K0 EEPROM Source Program 00 10 0D 02 9...

Page 424: ...cted to CORAD0 and CORAD1 and set bits 1 and 3 COREN0 COREN1 of the correction control register CORCN to 1 4 Set the main program so that the program branches from the specified address of the internal expansion RAM F7FDH to the internal expansion RAM address where the corrected program is stored using the entire space branch instruction BR addr16 5 After the main program is started the fetch addr...

Page 425: ...V0UD 425 Figure 25 7 ROM Correction Operation No Yes Internal flash memory program start Does fetch address match with correction address Set correction status flag Correction branch branch to address F7FDH Correction program execution ROM correction ...

Page 426: ...agram When One Place Is Corrected Correction place Internal flash memory Internal flash memory JUMP FFFFH F7FFH F7FDH xxxxH 0000H 1 2 3 BR JUMP Correction program 1 Branches to address F7FDH when fetch address matches correction address 2 Branches to correction program 3 Returns to internal flash memory program Remark Area filled with diagonal lines Internal expansion RAM JUMP Correction program s...

Page 427: ...en fetch address matches correction address 2 Branches to branch destination judgment program 3 Branches to correction program 1 by branch destination judgment program BTCLR CORST0 xxxxH 4 Returns to internal flash memory program 5 Branches to address F7FDH when fetch address matches correction address 6 Branches to branch destination judgment program 7 Branches to correction program 2 by branch d...

Page 428: ...dress from the set address value 3 Do not set the address value of instruction immediately after the instruction that sets the correction enable flag COREN0 COREN1 to 1 to correction address register 0 or 1 CORAD0 CORAD1 the correction branch may not start 4 Do not set the address value in table area of table reference instruction CALLT instruction 0040H to 007FH and the address value in vector ta...

Page 429: ...024 bytes µPD780134 1024 bytes µPD780136 1024 bytes µPD780138 1024 bytes Internal expansion RAM capacity µPD78F0132H None µPD78F0133H None µPD78F0134H None µPD78F0136H 1024 bytes Note 1 µPD78F0138H 1024 bytes Note 1 µPD78F0138HD 1024 bytes Note 1 µPD78F0134 None µPD78F0138 1024 bytes Note 1 µPD780131 None µPD780132 None µPD780133 None µPD780134 None µPD780136 1024 bytes µPD780138 1024 bytes Pin 3 ...

Page 430: ...S Address FFF0H After reset CFH R W Symbol 7 6 5 4 3 2 1 0 IMS RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0 RAM2 RAM1 RAM0 Internal high speed RAM capacity selection 0 1 0 512 bytes 1 1 0 1024 bytes Other than above Setting prohibited ROM3 ROM2 ROM1 ROM0 Internal ROM capacity selection 0 0 1 0 8 KB 0 1 0 0 16 KB 0 1 1 0 24 KB 1 0 0 0 32 KB 1 1 0 0 48 KB 1 1 1 1 60 KB Other than above Setting prohibited Th...

Page 431: ...n in Table 26 3 Figure 26 2 Format of Internal Expansion RAM Size Switching Register IXS Address FFF4H After reset 0CH R W Symbol 7 6 5 4 3 2 1 0 IXS 0 0 0 IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 Internal expansion RAM capacity selection 0 1 1 0 0 0 bytes 0 1 0 1 0 1024 bytes Other than above Setting prohibited The IXS settings required to obtain the same memory map a...

Page 432: ...S With UART6 Signal Name I O Pin Function Pin Name Pin No Pin Name Pin No Pin Name Pin No SI RxD Input Receive signal SO10 P12 25 SO10 P12 25 TxD6 P13 24 SO TxD Output Transmit signal SI10 RxD0 P11 26 SI10 RxD0 P11 26 RxD6 P14 23 SCK Output Transfer clock SCK10 TxD0 P10 27 SCK10 TxD0 P10 27 Not needed Not needed X1 7 X1 7 X1 7 CLK Output Clock to 78K0 KE1 X2 Note 8 X2 Note 8 X2 Note 8 RESET Output...

Page 433: ...re 26 3 Example of Wiring Adapter for Flash Memory Writing in 3 Wire Serial I O CSI10 Mode GND VDD VDD2 LVDD SI SO SCK CLK RESET FLMD0 FLMD1 HS WRITER INTERFACE VDD 2 7 to 5 5 V GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ...

Page 434: ...iting in 3 Wire Serial I O CSI10 HS Mode GND VDD SI SO SCK CLK RESET FLMD0 FLMD1 HS WRITER INTERFACE VDD 2 7 to 5 5 V GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD2 LVDD ...

Page 435: ...emory Writing in UART UART6 Mode GND VDD SI SO SCK CLK RESET FLMD0 FLMD1 HS WRITER INTERFACE VDD 2 7 to 5 5 V GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD2 LVDD ...

Page 436: ... between the dedicated flash programmer and the 78K0 KE1 CSI10 or UART6 is used for manipulation such as writing and erasing To write the flash memory off board a dedicated program adapter FA series is necessary 26 5 Communication Mode Communication between the dedicated flash programmer and the 78K0 KE1 is established by serial communication via CSI10 or UART6 of the 78K0 KE1 1 CSI10 Transfer rat...

Page 437: ...SCK X1 CLK X2 H S Dedicated flash programmer PG FP4 Flash Pro4 Cxxxxxx Bxxxxx Axxxx XXX YYY XXXXX XXXXXX XXXX XXXX YYYY STATVE VDD EVDD AVREF VSS EVSS AVSS FLMD0 FLMD0 3 UART6 Transfer rate 4800 to 76800 bps Figure 26 9 Communication with Dedicated Flash Programmer UART6 78K0 KE1 FLMD1 VDD VSS RESET TxD6 RxD6 FLMD1 VDD GND RESET SI RxD SO TxD X1 CLK X2 Dedicated flash programmer PG FP4 Flash Pro4 ...

Page 438: ... voltage generation voltage monitoring VDD EVDD AVREF GND Ground VSS EVSS AVSS CLK Output Clock output to 78K0 KE1 X1 X2 Note RESET Output Reset signal RESET SI RxD Input Receive signal SO10 TxD6 SO TxD Output Transmit signal SI10 RxD6 SCK Output Transfer clock SCK10 H S Input Handshake signal HS Note When using the clock out of the flash programmer connect CLK of the programmer to X1 and connect ...

Page 439: ...rmal operation mode 0 V is input to the FLMD0 pin In the flash memory programming mode the VDD write voltage is supplied to the FLMD0 pin An FLMD0 pin connection example is shown below Figure 26 10 FLMD0 Pin Connection Example FLMD0 Dedicated flash programmer connection pin 78K0 KE1 26 6 2 FLMD1 pin When 0 V is input to the FLMD0 pin the FLMD1 pin does not function When VDD is supplied to the FLMD...

Page 440: ...vice does not malfunction 1 Signal collision If the dedicated flash programmer output is connected to a pin input of a serial interface connected to another device output signal collision takes place To avoid this collision either isolate the connection with the other device or make the other device go into an output high impedance state Figure 26 12 Signal Collision Input Pin of Serial Interface ...

Page 441: ...isolate the connection with the other device Figure 26 13 Malfunction of Other Device Pin Dedicated flash programmer connection pin Other device Input pin If the signal output by the 78K0 KE1 in the flash memory programming mode affects the other device isolate the signal of the other device Pin Dedicated flash programmer connection pin Other device Input pin If the signal output by the dedicated ...

Page 442: ... 78K0 KE1 26 6 5 Port pins When the flash memory programming mode is set all the pins not used for flash memory programming enter the same status as that immediately after reset If external devices connected to the ports do not recognize the port status immediately after reset the port pin must be connected to VDD or VSS via a resistor 26 6 6 Other signal pins Connect X1 and X2 in the same status ...

Page 443: ...7 1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory Figure 26 15 Flash Memory Manipulation Procedure Start Selecting communication mode Manipulate flash memory End Yes FLMD0 pulse supply No End Flash memory programming mode is set ...

Page 444: ...pin to VDD and clear the reset signal Change the mode by using a jumper when writing the flash memory on board Figure 26 16 Flash Memory Programming Mode VDD RESET 5 5 V 0 V VDD 0 V Flash memory programming mode VDD 0 V FLMD0 FLMD0 pulse Hi Z VDD 0 V FLMD1 Table 26 7 Relationship Between FLMD0 FLMD1 Pins and Operation Mode After Reset Release FLMD0 FLMD1 Operation Mode 0 Any Normal operation mode ...

Page 445: ... 4800 to 76800 bpsNotes 2 3 TxD6 RxD6 0 3 wire serial I O CSI10 SIO ch0 200 kHz to 2 MHzNote 2 SO10 SI10 SCK10 8 3 wire serial I O with handshake supported CSI10 HS SIO H S 200 kHz to 2 MHzNote 2 Optional 2 MHz to 16 MHz 1 0 SO10 SI10 SCK10 HS P15 11 Notes 1 Selection items for Standard settings on Flashpro IV 2 The possible setting range differs depending on the voltage For details refer to the c...

Page 446: ...es the contents of the entire memory Blank check Batch blank check command Checks the erasure status of the entire memory High speed write command Writes data by specifying the write address and number of bytes to be written and executes a verify check Data write Successive write command Writes data from the address following that of the high speed write command executed immediately before and exe...

Page 447: ...ocedure of self programming is illustrated below Remark For details of the self programming function refer to the 78K0 Kx1 Flash Memory Self Programming User s Manual under preparation Figure 26 18 Self Programming Procedure Mask interrupts again FLSPM1 FLSPM0 0 1 Secure entry RAM area Mask all interrupts FLMD0 pin High level CALL 8100H Set parameters to entry RAM Start self programming Read param...

Page 448: ...C This register is used to enable or disable writing or erasing of the flash memory and to set the operation mode during self programming FLPMC can be written only in a specific sequence see 26 8 1 2 Flash protect command register PFCMD so that the application system does not stop inadvertently due to malfunction caused by noise or program hang up FLPMC can be set by a 1 bit or 8 bit memory manipu...

Page 449: ...Notes 1 Differs depending on the operation mode User mode 08H On board mode 0CH 2 Bit 2 FWEPR is read only 3 For actual writing erasing the FLMD0 pin must be high FWEPR 1 as well as FWEDIS 0 FWEDIS FWEPR Enable or disable of flash memory writing erasing 0 1 Writing erasing enabled Other than above Writing erasing disabled 4 The user ROM flash memory or firmware ROM can be selected by FLSPM1 and FL...

Page 450: ...annot be written illegally Occurrence of an illegal store operation can be checked by bit 0 FPRERR of the flash status register PFS A5H must be written to PFCMD each time the value of FLPMC is changed PFCMD can be set by an 8 bit memory manipulation instruction RESET input makes this register undefined Figure 26 20 Format of Flash Protect Command Register PFCMD REG7 Symbol PFCMD REG6 REG5 REG4 REG...

Page 451: ...alue of the value to be set to FLPMC is written by the first store instruction after 2 If the first store instruction operation after 3 is on a peripheral register other than FLPMC If a value other than the value to be set to FLPMC value written in 2 is written by the first store instruction after 3 Remark The numbers in angle brackets above correspond to the those in 2 Flash protect command regis...

Page 452: ...Consequently the above area to be swapped is used as a boot area and the program is executed correctly Figure 26 22 shows an image of the boot swap function Note The boot flag is controlled by the flash memory control firmware of the 78K0 KE1 Figure 26 22 Image of Boot Swap Function 1 If boot swap is not supported User program User program User program Boot program XXXXH 0000H User program User pr...

Page 453: ... cluster 1 in the figure are exchanged Figure 26 23 Memory Map and Boot Area 1 6 1 µPD78F0132H FF00H FEFFH FEE0H FEDFH FD00H FCFFH 4000H 3FFFH 1000H 0FFFH 2000H 1FFFH Boot cluster 0 4096 8 bits Boot cluster 1 4096 8 bits 8192 8 bits Special function registers SFR 256 8 bits General purpose registers 32 8 bits Flash memory 16384 8 bits Internal high speed RAM 512 8 bits Reserved Data memory space P...

Page 454: ...FEDFH FB00H FAFFH 6000H 5FFFH 1000H 0FFFH 2000H 1FFFH Boot cluster 0 4096 8 bits Boot cluster 1 4096 8 bits 16384 8 bits Special function registers SFR 256 8 bits General purpose registers 32 8 bits Flash memory 24576 8 bits Internal high speed RAM 1024 8 bits Reserved Data memory space Program memory space 0000H 0000H 5FFFH FFFFH ...

Page 455: ...its Internal high speed RAM 1024 8 bits General purpose registers 32 8 bits Reserved Flash memory 32768 8 bits Program memory space Data memory space H 0 0 0 0 H F F F 7 H 0 0 0 8 H F F A F H 0 0 B F H F D E F H 0 E E F H F F E F H 0 0 F F H F F F F 1000H 0FFFH 2000H 1FFFH Boot cluster 0 4096 8 bits Boot cluster 1 4096 8 bits 24576 8 bits 0000H 7FFFH ...

Page 456: ...H 0000H Special function registers SFR 256 8 bits Internal high speed RAM 1024 8 bits General purpose registers 32 8 bits Reserved Flash memory 49152 8 bits Program memory space Data memory space Reserved Internal expansion RAM 1024 8 bits 1000H 0FFFH 2000H 1FFFH Boot cluster 0 4096 8 bits Boot cluster 1 4096 8 bits 40960 8 bits 0000H BFFFH RAM space in which instructions can be fetched ...

Page 457: ...H 0000H Special function registers SFR 256 8 bits Internal high speed RAM 1024 8 bits General purpose registers 32 8 bits Reserved Flash memory 61440 8 bits Program memory space Data memory space Reserved Internal expansion RAM 1024 8 bits 1000H 0FFFH 2000H 1FFFH Boot cluster 0 4096 8 bits Boot cluster 1 4096 8 bits 53248 8 bits 0000H EFFFH RAM space in which instructions can be fetched ...

Page 458: ...l expansion RAM 1024 8 bits Reserved Reserved FB00H FAFFH F800H F7FFH F400H F3FFH RAM space in which instructions can be fetched Note 2 Note 1 Boot cluster 0 4096 8 bits 1000H 0FFFH 0000H Boot cluster 1 4096 8 bits 2000H 1FFFH 53248 8 bits EFFFH Program memory space Notes 1 During on chip debugging 9 bytes of this area are used as the user data backup area for communication 2 During on chip debugg...

Page 459: ...autions 1 Be sure to pull down P31 after reset to prevent malfunction 2 When using P31 for the on chip debug function it is recommended not to use P31 for any purpose other than on chip debugging or to control P31 with an external circuit using P130 that outputs a pseudo CPU reset signal Remarks 1 Only the ES emulation sample version is available for the µPD78F0138HD Use this product for program e...

Page 460: ...ng a label be sure to write the and symbols For operand register identifiers r and rp either function names X A C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can be used for specification Table 28 1 Operand Identifiers and Specification Methods Identifier Specification Method r rp sfr sfrp X R0 A R1 C R2 B R3 E R4 D R5 L R6 H R7 AX RP0 BC RP1 DE RP2 HL RP3 Special fu...

Page 461: ... word CY Carry flag AC Auxiliary carry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag Memory contents indicated by address or register contents in parentheses XH XL Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data addr16 16 bit immediate data or label jdisp8 Signed 8 bit data displ...

Page 462: ... HL A A HL byte 2 8 9 A HL byte HL byte A 2 8 9 HL byte A A HL B 1 6 7 A HL B HL B A 1 6 7 HL B A A HL C 1 6 7 A HL C MOV HL C A 1 6 7 HL C A A r Note 3 1 2 A r A saddr 2 4 6 A saddr A sfr 2 6 A sfr A addr16 3 8 10 A addr16 A DE 1 4 6 A DE A HL 1 4 6 A HL A HL byte 2 8 10 A HL byte A HL B 2 8 10 A HL B 8 bit data transfer XCH A HL C 2 8 10 A HL C Notes 1 When the internal high speed RAM area is ac...

Page 463: ... CY A addr16 A HL 1 4 5 A CY A HL A HL byte 2 8 9 A CY A HL byte A HL B 2 8 9 A CY A HL B ADD A HL C 2 8 9 A CY A HL C A byte 2 4 A CY A byte CY saddr byte 3 6 8 saddr CY saddr byte CY A r Note 4 2 4 A CY A r CY r A 2 4 r CY r A CY A saddr 2 4 5 A CY A saddr CY A addr16 3 8 9 A CY A addr16 C A HL 1 4 5 A CY A HL CY A HL byte 2 8 9 A CY A HL byte CY A HL B 2 8 9 A CY A HL B CY 8 bit operation ADDC ...

Page 464: ...dr16 3 8 9 A CY A addr16 CY A HL 1 4 5 A CY A HL CY A HL byte 2 8 9 A CY A HL byte CY A HL B 2 8 9 A CY A HL B CY SUBC A HL C 2 8 9 A CY A HL C CY A byte 2 4 A A byte saddr byte 3 6 8 saddr saddr byte A r Note 3 2 4 A A r r A 2 4 r r A A saddr 2 4 5 A A saddr A addr16 3 8 9 A A addr16 A HL 1 4 5 A A HL A HL byte 2 8 9 A A HL byte A HL B 2 8 9 A A HL B 8 bit operation AND A HL C 2 8 9 A A HL C Note...

Page 465: ...6 3 8 9 A A addr16 A HL 1 4 5 A A HL A HL byte 2 8 9 A A HL byte A HL B 2 8 9 A A HL B XOR A HL C 2 8 9 A A HL C A byte 2 4 A byte saddr byte 3 6 8 saddr byte A r Note 3 2 4 A r r A 2 4 r A A saddr 2 4 5 A saddr A addr16 3 8 9 A addr16 A HL 1 4 5 A HL A HL byte 2 8 9 A HL byte A HL B 2 8 9 A HL B 8 bit operation CMP A HL C 2 8 9 A HL C Notes 1 When the internal high speed RAM area is accessed or f...

Page 466: ...HL 3 0 HL 7 4 A3 0 HL 3 0 HL 7 4 Rotate ROL4 HL 2 10 12 A3 0 HL 7 4 HL 3 0 A3 0 HL 7 4 HL 3 0 ADJBA 2 4 Decimal Adjust Accumulator after Addition BCD adjustment ADJBS 2 4 Decimal Adjust Accumulator after Subtract CY saddr bit 3 6 7 CY saddr bit CY sfr bit 3 7 CY sfr bit CY A bit 2 4 CY A bit CY PSW bit 3 7 CY PSW bit CY HL bit 2 6 7 CY HL bit saddr bit CY 3 6 8 saddr bit CY sfr bit CY 3 8 sfr bit ...

Page 467: ...CY CY A bit CY PSW bit 3 7 CY CY PSW bit XOR1 CY HL bit 2 6 7 CY CY HL bit saddr bit 2 4 6 saddr bit 1 sfr bit 3 8 sfr bit 1 A bit 2 4 A bit 1 PSW bit 2 6 PSW bit 1 SET1 HL bit 2 6 8 HL bit 1 saddr bit 2 4 6 saddr bit 0 sfr bit 3 8 sfr bit 0 A bit 2 4 A bit 0 PSW bit 2 6 PSW bit 0 CLR1 HL bit 2 6 8 HL bit 0 SET1 CY 1 2 CY 1 1 CLR1 CY 1 2 CY 0 0 Bit manipulate NOT1 CY 1 2 CY CY Notes 1 When the int...

Page 468: ...1 PSW SP SP 1 PUSH rp 1 4 SP 1 rpH SP 2 rpL SP SP 2 PSW 1 2 PSW SP SP SP 1 R R R POP rp 1 4 rpH SP 1 rpL SP SP SP 2 SP word 4 10 SP word SP AX 2 8 SP AX Stack manipulate MOVW AX SP 2 8 AX SP addr16 3 6 PC addr16 addr16 2 6 PC PC 2 jdisp8 Unconditional branch BR AX 2 8 PCH A PCL X BC addr16 2 6 PC PC 2 jdisp8 if CY 1 BNC addr16 2 6 PC PC 2 jdisp8 if CY 0 BZ addr16 2 6 PC PC 2 jdisp8 if Z 1 Conditio...

Page 469: ...C PC 4 jdisp8 if sfr bit 1 then reset sfr bit A bit addr16 3 8 PC PC 3 jdisp8 if A bit 1 then reset A bit PSW bit addr16 4 12 PC PC 4 jdisp8 if PSW bit 1 then reset PSW bit BTCLR HL bit addr16 3 10 12 PC PC 3 jdisp8 if HL bit 1 then reset HL bit B addr16 2 6 B B 1 then PC PC 2 jdisp8 if B 0 C addr16 2 6 C C 1 then PC PC 2 jdisp8 if C 0 Conditional branch DBNZ Saddr addr16 3 8 10 saddr saddr 1 then...

Page 470: ...None A ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP ROR ROL RORC ROLC r MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP INC DEC B C DBNZ sfr MOV MOV saddr MOV ADD ADDC SUB SUBC AND OR XOR CMP MO...

Page 471: ...VW MOVW addr16 MOVW SP MOVW MOVW Note Only when rp BC DE HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand First Operand A bit sfr bit saddr bit PSW bit HL bit CY addr16 None A bit MOV1 BT BF BTCLR SET1 CLR1 sfr bit MOV1 BT BF BTCLR SET1 CLR1 saddr bit MOV1 BT BF BTCLR SET1 CLR1 PSW bit MOV1 BT BF BTCLR SET1 CLR1 HL bit MOV1 BT BF BTCLR SET1 CLR1 CY MO...

Page 472: ...tructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand First Operand AX addr16 addr11 addr5 addr16 Basic instruction BR CALL BR CALLF CALLT BR BC BNC BZ BNZ Compound instruction BT BF BTCLR DBNZ 5 Other instructions ADJBA ADJBS BRK RET RETI RETB SEL NOP EI DI HALT STOP ...

Page 473: ...30 P140 P141 30 mA P00 to P06 P10 to P17 P30 to P33 P40 to P43 P50 to P53 P70 to P77 P120 P130 P140 P141 20 mA Per pin P60 to P63 30 mA P00 to P06 P40 to P43 P50 to P53 P70 to P77 35 mA Output current low IOL Total of all pins 70 mA P10 to P17 P30 to P33 P60 to P63 P120 P130 P140 P141 35 mA In normal operation mode 40 to 85 Operating ambient temperature TA In flash memory programming mode 10 to 65...

Page 474: ...icates only oscillator characteristics Refer to AC Characteristics for instruction execution time Cautions 1 When using the high speed system clock oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the...

Page 475: ...33 CSTCE10M0G55 R0 10 0 Internal 33 Internal 33 CSTCE12M0G55 R0 12 0 Internal 33 Internal 33 CSTCE13M0V53 R0 13 0 Internal 15 Internal 15 CSTCE14M0V53 R0 14 0 Internal 15 Internal 15 Murata Mfg CSTCE16M0V53 R0 SMD 16 0 Internal 15 Internal 15 2 5 5 5 Caution The oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator manufacturer If it i...

Page 476: ...stem clock oscillator wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the sam...

Page 477: ... P14 P16 P17 P30 to P33 P70 to P77 P120 P140 P141 RESET 2 0 V VDD 2 7 V 0 85VDD VDD V 2 7 V VDD 5 5 V 0 7AVREF AVREF V VIH3 P20 to P27 Note 2 2 0 V VDD 2 7 V 0 8AVREF AVREF V 2 7 V VDD 5 5 V 0 7VDD VDD V VIH4 P60 P61 2 0 V VDD 2 7 V 0 8VDD VDD V 2 7 V VDD 5 5 V 0 7VDD 12 V VIH5 P62 P63 2 0 V VDD 2 7 V 0 8VDD 12 V 2 7 V VDD 5 5 V VDD 0 5 VDD V Input voltage high VIH6 X1 X2 XT1 XT2 2 0 V VDD 2 7 V V...

Page 478: ...ET 3 µA ILIH1 VI AVREF P20 to P27 3 µA ILIH2 VI VDD X1 X2 Note 2 XT1 XT2 Note 2 20 µA Input leakage current high ILIH3 VI 12 V P62 P63 N ch open drain 3 µA ILIL1 P00 to P06 P10 to P17 P20 to P27 P30 to P33 P40 to P43 P50 to P53 P60 P61 P70 to P77 P120 P140 P141 RESET 3 µA ILIL2 X1 X2 Note 2 XT1 XT2 Note 2 20 µA Input leakage current low ILIL3 VI 0 V P62 P63 N ch open drain 3 Note 3 µA Output leaka...

Page 479: ...A IDD2 Crystal ceramic oscillation HALT mode fXP 5 MHz VDD 3 0 V 10 When peripheral functions are operating 3 5 mA VDD 5 0 V 10 0 9 3 6 mA IDD3 Ring OSC operating mode Note 5 VDD 3 0 V 10 0 4 1 6 mA VDD 5 0 V 10 0 4 1 6 mA IDD4 Ring OSC HALT mode Note 5 VDD 3 0 V 10 0 25 1 0 mA VDD 5 0 V 10 50 0 100 µA IDD5 32 768 kHz crystal oscillation operating mode Notes 5 6 VDD 3 0 V 10 30 0 60 0 µA VDD 5 0 V...

Page 480: ...VDD 2 7 V 2 fsam 0 5 Note 3 µs 4 0 V VDD 5 5 V 10 MHz 2 7 V VDD 4 0 V 5 MHz TI50 TI51 input frequency fTI5 2 5 V VDD 2 7 V 2 5 MHz 4 0 V VDD 5 5 V 50 ns 2 7 V VDD 4 0 V 100 ns TI50 TI51 input high level width low level width tTIH5 tTIL5 2 5 V VDD 2 7 V 200 ns 2 7 V VDD 5 5 V 1 µs Interrupt input high level width low level width tINTH tINTL 2 0 V VDD 2 7 V 2 µs 4 0 V VDD 5 5 V 50 ns 2 7 V VDD 4 0 V...

Page 481: ... System Clock Operation 5 0 1 0 2 0 0 4 0 2 0 1 Supply voltage VDD V Cycle time T CY s 0 10 0 1 0 2 0 3 0 4 0 5 0 6 0 5 5 Guaranteed operation range 20 0 16 0 33 3 4 17 0 238 0 125 3 5 2 5 µ Remark The values indicated by the shaded section are only when the Ring OSC clock is selected ...

Page 482: ...h low level width tKH1 tKL1 2 5 V VDD 2 7 V tKCY1 2 50 ns 2 7 V VDD 5 5 V 30 ns SI1n setup time to SCK1n tSIK1 2 5 V VDD 2 7 V 70 ns 2 7 V VDD 5 5 V 30 ns SI1n hold time from SCK1n tKSI1 2 5 V VDD 2 7 V 70 ns 2 7 V VDD 5 5 V 30 ns Delay time from SCK1n to SO1n output tKSO1 C 100 pF Note 2 5 V VDD 2 7 V 120 ns Note C is the load capacitance of the SCK1n and SO1n output lines d 3 wire serial I O mod...

Page 483: ...DD Test points 0 8VDD 0 2VDD Clock Timing X1 VIH6 MIN VIL6 MAX 1 fXP tXPL tXPH 1 fXT tXTL tXTH XT1 VIH6 MIN VIL6 MAX TI Timing TI000 TI010 TI001Note TI011Note tTIL0 tTIH0 TI50 TI51 1 fTI5 tTIL5 tTIH5 Interrupt Request Input Timing INTP0 to INTP7 tINTL tINTH Note µPD78F0133H 78F0134H 78F0136H 78F0138H and 78F0138HD only ...

Page 484: ... U16899EJ2V0UD 484 RESET Input Timing RESET tRSL Serial Transfer Timing 3 wire serial I O mode SI1n SO1n tKCYm tKLm tKHm tSIKm tKSIm Input data tKSOm Output data SCK1n Remark m 1 2 n 0 µPD78F0132H n 0 1 µPD78F0133H 78F0134H 78F0136H 78F0138H 78F0138HD ...

Page 485: ... tCONV 2 5 V AVREF 2 7 V 48 100 µs 4 0 V AVREF 5 5 V 0 4 FSR 2 7 V AVREF 4 0 V 0 6 FSR Zero scale error Notes 1 2 2 5 V AVREF 2 7 V 1 2 FSR 4 0 V AVREF 5 5 V 0 4 FSR 2 7 V AVREF 4 0 V 0 6 FSR Full scale error Notes 1 2 2 5 V AVREF 2 7 V 1 2 FSR 4 0 V AVREF 5 5 V 2 5 LSB 2 7 V AVREF 4 0 V 4 5 LSB Integral non linearity error Note 1 2 5 V AVREF 2 7 V 8 5 LSB 4 0 V AVREF 5 5 V 1 5 LSB 2 7 V AVREF 4 0...

Page 486: ...s Response delay time 1 Note 1 tPTHD When power supply rises after reaching detection voltage MAX 3 0 ms Response delay time 2 Note 2 tPD When VDD falls 1 0 ms Minimum pulse width tPW 0 2 ms Notes 1 Time required from voltage detection to reset release 2 Time required from voltage detection to internal reset output POC Circuit Timing Supply voltage VDD Time Detection voltage MIN Detection voltage ...

Page 487: ...Operation stabilization wait time Note 2 tLWAIT 0 1 0 2 ms Notes 1 Time required from voltage detection to interrupt output or internal reset output 2 Time required from setting LVION to 1 to operation stabilization Remarks 1 VLVI0 VLVI1 VLVI2 VLVI3 VLVI4 VLVI5 VLVI6 VLVI7 VLVI8 VLVI9 2 VPOC VLVIm m 0 to 9 LVI Circuit Timing Supply voltage VDD Time Detection voltage MIN Detection voltage TYP Detec...

Page 488: ...e Twrwa 50 500 µs Number of rewrites per chip Note 3 Cerwr 1 erase 1 write after erase 1 rewrite Note 4 100 Times Notes 1 Time required for one erasure execution 2 The total time for repetition of the unit erase time 255 times max until the data is erased completely Note that the prewrite time and the erase verify time writeback time before data erasure are not included 3 Number of rewrites per bl...

Page 489: ...ASTIC LQFP 10x10 ITEM MILLIMETERS A B D G 12 0 0 2 10 0 0 2 1 25 12 0 0 2 H 0 22 0 05 C 10 0 0 2 F 1 25 I J K 0 08 0 5 T P 1 0 0 2 L 0 5 P 1 4 Q 0 1 0 05 T 0 25 S 1 5 0 10 U 0 6 0 15 S64GB 50 8EU 2 R 3 4 3 N 0 08 M 0 17 0 03 0 07 A B C D U NOTE Each lead centerline is located within 0 08 mm of its true position T P at maximum material condition ...

Page 490: ... position T P at maximum material condition ITEM MILLIMETERS A B D G 17 2 0 2 14 0 0 2 0 8 T P 1 0 J 17 2 0 2 K C 14 0 0 2 I 0 20 1 6 0 2 L 0 8 F 1 0 N P Q 0 10 1 4 0 1 0 127 0 075 U 0 886 0 15 R S 3 1 7 MAX T 0 25 P64GC 80 8BS H 0 37 0 08 0 07 M 0 17 0 03 0 06 S N J T detail of lead end C D A B K M I S P R L U Q G F M H 4 3 1 64 49 17 32 16 48 33 S ...

Page 491: ... C 12 0 0 2 D F 1 125 14 0 0 2 B 12 0 0 2 N 0 10 P Q 0 1 0 05 1 0 S R 3 4 3 R H K J Q G I S P detail of lead end NOTE Each lead centerline is located within 0 13 mm of its true position T P at maximum material condition M H 0 32 0 06 0 10 I 0 13 J K 1 0 0 2 0 65 T P L 0 5 M 0 17 0 03 0 07 P64GK 65 9ET 3 T U 0 6 0 15 0 25 F M A B C D N T L U 1 1 0 1 ...

Page 492: ...6 ITEM DIMENSIONS E w 6 00 0 10 0 20 y 0 20 0 10 y1 ZD 0 725 0 08 x D 6 00 0 10 e 0 65 A 1 43 0 10 A1 0 30 0 05 0 40 0 05 A2 1 13 b P64F1 65 BA2 ZE 0 725 A1 S y1 SD 0 325 SE 0 325 INDEX MARK w S A w S B b e x S AB M A ZD SD SE ZE B H G F E D C B A 8 7 6 5 4 3 2 1 A2 S y S A E D UNIT mm ...

Page 493: ...f its true position T P at maximum material condition ITEM MILLIMETERS A B D G 14 8 0 4 12 0 0 2 0 13 1 125 I 14 8 0 4 J C 12 0 0 2 H 0 32 0 08 0 65 T P K 1 4 0 2 L 0 6 0 2 F 1 125 P64GK 65 8A8 3 N P Q 0 10 1 4 0 1 0 125 0 075 R S 5 5 1 7 MAX M 0 17 0 08 0 07 48 49 32 64 1 17 16 33 S S N J detail of lead end C D A B R K M L P I S Q G F M H ...

Page 494: ...face Mounting Type Soldering Conditions 64 pin plastic LQFP 10 10 µPD78F0132HGB 8EU 78F0133HGB 8EU 78F0134HGB 8EU µPD78F0136HGB 8EU 78F0138HGB 8EU 64 pin plastic LQFP 14 14 µPD78F0132HGC 8BS 78F0133HGC 8BS 78F0134HGC 8BS µPD78F0136HGC 8BS 78F0138HGC 8BS 64 pin plastic TQFP 12 12 µPD78F0132HGK 9ET 78F0133HGK 9ET 78F0134HGK 9ET µPD78F0136HGK 9ET 78F0138HGK 9ET Soldering Method Soldering Conditions R...

Page 495: ...egal data may be passed if an access to the CPU conflicts with an access to the peripheral hardware When accessing the peripheral hardware that may cause a conflict therefore the CPU repeatedly executes processing until the correct data is passed As a result the CPU does not start the next instruction processing but waits If this happens the number of execution clocks of an instruction increases b...

Page 496: ...R Read 1 to 5 clocks when ADM 5 flag 1 1 to 9 clocks when ADM 5 flag 0 A D converter Calculating maximum number of wait clocks 1 fMACRO 2 1 fCPU 1 The result after the decimal point is truncated if it is less than tCPUL after it has been multiplied by 1 fCPU and is rounded up if it exceeds tCPUL fMACRO Macro operating frequency When bit 5 FR2 of ADM 1 fX 2 when bit 5 FR2 of ADM 0 fX 2 2 fCPU CPU c...

Page 497: ...D converter Table 32 2 Number of Wait Clocks and Number of Execution Clocks on Occurrence of Wait A D Converter On execution of MOV ADM A MOV ADS A or MOV A ADCR When fX 10 MHz tCPUL 50 ns Value of Bit 5 FR2 of ADM Register fCPU Number of Wait Clocks Number of Execution Clocks fX 9 clocks 14 clocks fX 2 5 clocks 10 clocks fX 2 2 3 clocks 8 clocks fX 2 3 2 clocks 7 clocks 0 fX 2 4 0 clocks 1 clock ...

Page 498: ...ess otherwise specified products supported by IBM PC ATTM compatibles are compatible with PC98 NX series computers When using PC98 NX series computers refer to the explanation for IBM PC AT compatibles WindowsTM Unless otherwise specified Windows means the following OSs Windows 3 1 Windows 95 Windows 98 Windows NTTM Ver 4 0 Windows 2000 Windows XP Caution For the development tools of the 78K0 KE1 ...

Page 499: ...face cable Conversion socket or conversion adapter Target system Flash programmer Flash memory writing adapter Flash memory Software package Project manager Windows only Note 2 Software package Flash memory writing environment Control software Notes 1 The C library source file is not included in the software package 2 The project manager PM plus is included in the assembler package PM plus is only...

Page 500: ... PC or EWS USB interface cable Target connector Target system Flash programmer Flash memory writing adapter Flash memory Software package Project manager Windows only Note 2 Software package Flash memory writing environment Control software Notes 1 The C library source file is not included in the software package 2 The project manager PM plus is included in the assembler package PM plus is only us...

Page 501: ...µS RA78K0 This compiler converts programs written in C language into object codes executable with a microcontroller This compiler should be used in combination with an assembler package and device file both sold separately Precaution when using CC78K0 in PC environment This C compiler package is a DOS based application It can also be used in Windows however by using the project manager included in...

Page 502: ...user program such as starting the editor building and starting the debugger can be performed from PM plus Caution PM plus is included in the assembler package RA78K0 It can only be used in Windows A 4 Flash Memory Writing Tools Flashpro IV part number FL PR4 PG FP4 Flash programmer Flash programmer dedicated to microcontrollers with on chip flash memory PG FPL Flash memory programmer Flash memory ...

Page 503: ...1T QB 64GK YQ 01T YQ connector This connector is used to connect the target connector to the exchange adapter QB 64GB YQ 01T For 64 pin plastic LQFP GB 8EU type QB 64GC YQ 01T For 64 pin plastic LQFP GC 8BS type QB 64GK YQ 01T For 64 pin plastic TQFP GK 9ET type QB 64GB HQ 01T QB 64GC HQ 01T QB 64GK HQ 01T QB 64GK HQ 02T Mount adapter This adapter is used to mount the target device onto the target...

Page 504: ...ormance testing on an independent basis from hardware development thereby providing higher development efficiency and software quality SM for 78K0 should be used in combination with the device file DF780138 sold separately SM for 78K0 Note System simulator Part number µS SM780000 This debugger supports the in circuit emulators for the 78K0 Kx1 Series The ID78K0 QB is Windows based software It has ...

Page 505: ...ng height restrictions when using the QB 78K0KX1H a For 64 pin GB package Figure B 1 Restricted Areas on Target System 64 Pin GB Package 15 10 5 13 375 10 15 10 5 17 375 10 Exchange adapter area Components up to 17 45 mm in height can be mounted Note Emulation probe tip area Components up to 24 45 mm in height can be mounted Note Note Height can be regulated by using space adapters each adds 2 4 m...

Page 506: ...be tip area Components up to 24 45 mm in height can be mountedNote Note Height can be regulated by using space adapters each adds 2 4 mm c For 64 pin GC package Figure B 3 Restricted Areas on Target System 64 Pin GC Package 15 11 85 13 375 10 15 11 85 17 375 10 Exchange adapter area Components up to 17 45 mm in height can be mountedNote Emulation probe tip area Components up to 24 45 mm in height ...

Page 507: ...e compare control register 00 CRC00 145 Capture compare control register 01 CRC01 146 Clock monitor mode register CLM 398 Clock output selection register CKS 243 Clock selection register 6 CKSR6 299 Correction address register 0 CORAD0 420 Correction address register 1 CORAD1 420 Correction control register CORCN 421 E 8 bit timer compare register 50 CR50 183 8 bit timer compare register 51 CR51 1...

Page 508: ...61 K Key return mode register KRM 375 L Low voltage detection level selection register LVIS 410 Low voltage detection register LVIM 409 M Main clock mode register MCM 114 Main OSC control register MOC 115 Multiplication division data register A0 MDA0H MDA0L 348 Multiplication division data register B0 MDB0 349 Multiplier divider control register 0 DMUC0 350 O Oscillation stabilization time counter...

Page 509: ...ption register 12 PU12 107 Pull up resistor option register 14 PU14 107 Pull up resistor option register 3 PU3 107 Pull up resistor option register 4 PU4 107 Pull up resistor option register 5 PU5 107 Pull up resistor option register 7 PU7 107 R Receive buffer register 0 RXB0 270 Receive buffer register 6 RXB6 294 Receive shift register 0 RXS0 270 Remainder data register 0 SDR0 348 Reset control f...

Page 510: ...00 TOC00 146 16 bit timer output control register 01 TOC01 146 T Timer clock selection register 50 TCL50 184 Timer clock selection register 51 TCL51 184 Transmit buffer register 10 SOTB10 328 Transmit buffer register 11 SOTB11 328 Transmit buffer register 6 TXB6 294 Transmit shift register 0 TXS0 270 W Watch timer operation mode register WTM 226 Watchdog timer enable register WDTE 235 Watchdog tim...

Page 511: ... Clock monitor mode register 398 CMP00 8 bit timer H compare register 00 201 CMP01 8 bit timer H compare register 01 201 CMP10 8 bit timer H compare register 10 201 CMP11 8 bit timer H compare register 11 201 CORAD0 Correction address register 0 420 CORAD1 Correction address register 1 420 CORCN Correction control register 421 CR000 16 bit timer capture compare register 000 139 CR001 16 bit timer ...

Page 512: ... register A0 348 MDA0L Multiplication division data register A0 348 MDB0 Multiplication division data register B0 349 MK0H Interrupt mask flag register 0H 363 MK0L Interrupt mask flag register 0L 363 MK1H Interrupt mask flag register 1H 363 MK1L Interrupt mask flag register 1L 363 MOC Main OSC control register 115 O OSTC Oscillation stabilization time counter status register 116 378 OSTS Oscillati...

Page 513: ...resistor option register 0 107 PU1 Pull up resistor option register 1 107 PU12 Pull up resistor option register 12 107 PU14 Pull up resistor option register 14 107 PU3 Pull up resistor option register 3 107 PU4 Pull up resistor option register 4 107 PU5 Pull up resistor option register 5 107 PU7 Pull up resistor option register 7 107 R RCM Ring OSC mode register 113 RESF Reset control flag registe...

Page 514: ...ter 51 187 TMCYC1 8 bit timer H carrier control register 1 206 TMHMD0 8 bit timer H mode register 0 202 TMHMD1 8 bit timer H mode register 1 202 TOC00 16 bit timer output control register 00 146 TOC01 16 bit timer output control register 01 146 TXB6 Transmit buffer register 6 294 TXS0 Transmit shift register 0 270 W WDTE Watchdog timer enable register 235 WDTM Watchdog timer mode register 234 WTM ...

Page 515: ...0081H to 0083H in the µPD78F0138HD cannot be used p 47 When replacing the µPD78F0134H with the µPD78F0138HD note that the area from 0081H to 0083H in the µPD78F0138HD cannot be used p 48 When replacing the µPD78F0136H with the µPD78F0138HD note that the area from 0081H to 0083H in the µPD78F0138HD cannot be used p 49 Program area When replacing the µPD78F0138H with the µPD78F0138HD note that the a...

Page 516: ... mode register Set MCS 1 and MCM0 1 before switching subsystem clock operation to high speed system clock operation bit 4 CSS of the processor clock control register PCC is changed from 1 to 0 p 114 Main clock Make sure that bit 1 MCS of the main clock mode register MCM is 0 before setting MSTOP p 115 Subsystem clock MOC Main OSC control register To stop high speed system clock oscillation when th...

Page 517: ...n the Figures 5 8 and 5 9 to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the same potential as VSS Do not ground the capacitor to a ground pattern throug...

Page 518: ...gger p 141 Hard When CR01n is used as a capture register read data is undefined if the register read time and capture trigger input conflict the capture data itself is the correct value If count stop input and capture trigger input conflict the captured data is undefined p 141 CR01n 16 bit timer capture compare register 01n CR01n can be rewritten during TM0n operation For details see Caution 2 in ...

Page 519: ...ously p 147 TOC00 16 bit timer output control register 00 Perform 1 and 2 below in the following order not at the same time 1 Set TOC001 TOC004 TOE00 OSPE00 Timer output operation setting 2 Set LVS00 LVR00 Timer output F F setting p 147 Timer operation must be stopped before setting other than TOC014 p 148 If LVS01 and LVR01 are read 0 is read p 148 OSPT01 is automatically cleared after data is se...

Page 520: ...e trigger p 152 Soft If the TI001 or TI011 pin is high level immediately after system reset the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge s of the TI001 pin or TI011 pin to enable the operation of 16 bit timer counter 01 TM01 Care is therefore required when pulling up the TI001 or TI011 pin However if the TI001 or TI011...

Page 521: ...is is because 16 bit timer counter 0n TM0n is started asynchronously to the count clock p 177 16 bit timer capture compare register setting In the mode in which clear start occurs on a match between TM0n and CR00n set 16 bit timer capture compare register 00n CR00n to other than 0000H This means a 1 pulse count operation cannot be performed when 16 bit timer event counter 0n is used as an external...

Page 522: ...w does not occur p 179 If the TI00n pin valid edge is specified as the count clock a capture operation by the capture register specified as the trigger for the TI00n pin is not possible p 179 To ensure the reliability of the capture operation the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 0n PRM0n p 179 Capture operation The captu...

Page 523: ...1 TMC5n6 Operation mode setting 2 Set TOE5n to enable output Timer output enable 3 Set LVS5n LVR5n see Caution 1 Timer F F setting 4 Set TCE5n p 187 TMC5n 8 bit timer mode control register 5n Stop operation before rewriting TMC5n6 p 187 Interval timer square waveform output Do not write other values to CR5n during operation pp 189 192 In PWM mode make the CR5n rewrite interval 3 count clocks of th...

Page 524: ...ired to transfer the CMP1n register value after rewriting the register p 212 Be sure to set the CMP1n register when starting the timer count operation TMHEn 1 after the timer count operation was stopped TMHEn 0 be sure to set again even if setting the same value to the CMP1n register p 212 PWM output Make sure that the CMP1n register setting value M and CMP0n register setting value N are within th...

Page 525: ... 0 In addition the internal reset signal is not generated p 235 If a value other than ACH is written to WDTE an internal reset signal is generated If the source clock to the watchdog timer is stopped however an internal reset signal is generated when the source clock to the watchdog timer resumes operation p 235 If a 1 bit memory manipulation instruction is executed for WDTE an internal reset sign...

Page 526: ...it cycle is generated Do not write data to PFT when the CPU is operating on the subsystem clock and the high speed system clock is stopped For details see CHAPTER 32 CAUTIONS FOR WAIT p 253 Make sure the period of 1 to 3 is 14 µs or more p 259 It is no problem if the order of 1 and 2 is reversed p 259 1 can be omitted However do not use the first conversion result after 3 in this case p 259 A D co...

Page 527: ...VREF pin input impedance A series resistor string of several tens of kΩ is connected between the AVREF and AVSS pins Therefore if the output impedance of the reference voltage source is high this will result in a series connection to the series resistor string between the AVREF and AVSS pins resulting in a large reference voltage error p 263 Interrupt request flag ADIF The interrupt request flag A...

Page 528: ...ansmit shift register 0 Do not write the next transmit data to TXS0 before the transmission completion interrupt signal INTST0 is generated p 270 At startup set POWER0 to 1 and then set TXE0 to 1 To stop the operation clear TXE0 to 0 and then clear POWER0 to 0 p 272 At startup set POWER0 to 1 and then set RXE0 to 1 To stop the operation clear RXE0 to 0 and then clear POWER0 to 0 p 272 Set POWER0 t...

Page 529: ...e sure that the baud rate error during reception satisfies the range shown in 4 Permissible baud rate range during reception p 284 Chapter 13 Soft Serial interface UART0 Allowable baud rate range during reception Make sure that the baud rate error during reception is within the permissible error range by using the calculation expression shown below p 286 Hard The TXD6 output inversion function inv...

Page 530: ... the first transmit data first byte to the TXB6 register After that be sure to check that the TXBF6 flag is 0 If so write the next transmit data second byte to the TXB6 register If data is written to the TXB6 register while the TXBF6 flag is 1 the transmit data cannot be guaranteed p 298 Soft ASIF6 Asynchronous serial interface transmission status register 6 To initialize the transmission unit upo...

Page 531: ...LIN the continuous transmission function cannot be used Make sure that asynchronous serial interface transmission status register 6 ASIF6 is 00H before writing transmit data to transmit buffer register 6 TXB6 p 311 TXBF6 during continuous transmission Bit 1 of ASIF6 To transmit data continuously write the first transmit data first byte to the TXB6 register Be sure to check that the TXBF6 flag is 0...

Page 532: ...is divided and supplied as the serial clock At this time the operation of serial interface CSI10 is not guaranteed p 332 Do not write to CSIC10 while CSIE10 1 operation enabled p 332 Clear CKP10 to 0 to use P10 SCK10 TxD0 P11 SI10 RxD0 and P12 SO10 as general purpose port pins p 332 Soft CSIC10 Serial clock selection register 10 The phase type of the data clock is type 1 after reset p 332 Hard Whe...

Page 533: ...tion results are stored in multiplication division data register A0 MDA0 and remainder data register 0 SDR0 p 350 Chapter 16 Soft Multiplier divider DMUC Multiplier divider control register 0 If DMUE is cleared to 0 during operation processing while DMUE is 1 the operation processing is stopped To execute the operation again set multiplication division data register A0 MDA0 multiplication division...

Page 534: ...e can be used only when CPU is operating on the high speed system clock or Ring OSC clock HALT mode can be used when CPU is operating on the high speed system clock Ring OSC clock or subsystem clock However when the STOP instruction is executed during Ring OSC clock operation the high speed system clock oscillator stops but Ring OSC oscillator does not stop p 377 Hard When shifting to the STOP mod...

Page 535: ...by RESET input or interrupt generation p 379 Chapter 19 Soft Standby function STOP mode setting and operation status Because the interrupt request signal is used to release the standby mode if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset the standby mode is immediately released if set Thus the STOP mode is reset to the HALT mode immediately aft...

Page 536: ...processing in 3 p 411 When used as reset If supply voltage VDD detection voltage VLVI when LVIMD is set to 1 an internal reset signal is not generated p 411 Chapter 23 Soft Low voltage detector LVI Cautions for low voltage detector In a system where the supply voltage VDD fluctuates for a certain period in the vicinity of the LVI detection voltage VLVI the operation is as follows depending on how ...

Page 537: ...roducing it with the mask ROM version be sure to conduct sufficient evaluations for the commercial samples not engineering samples of the mask ROM versions p 429 IMS Internal memory size switching register The initial value of IMS is CFH Be sure to set each product to the values shown in Table 26 2 at initialization Also when using the 78K0 KE1 to evaluate the program of a mask ROM version of the ...

Page 538: ...r to be used p 474 Recommended oscillator constants The oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator manufacturer If it is necessary to optimize the oscillator characteristics in the actual application apply to the resonator manufacturer for evaluation on the implementation circuit The oscillation voltage and oscillation frequ...

Page 539: ...mat of 8 Bit Timer H Mode Register 0 TMHMD0 p 205 Modification of Note in Figure 8 6 Format of 8 Bit Timer H Mode Register 1 TMHMD1 p 231 Correction of Table 10 1 Loop Detection Time of Watchdog Timer p 244 Addition of Note to Figure 11 2 Format of Clock Output Selection Register CKS p 274 Modification of Note 1 in Figure 13 4 Format of Baud Rate Generator Control Register 0 BRGC0 p 299 Modificati...

Page 540: ...SION HISTORY User s Manual U16899EJ2V0UD 540 2 2 Page Description p 505 Revision of APPENDIX B NOTES ON TARGET SYSTEM DESIGN p 515 Addition of APPENDIX D LIST OF CAUTIONS p 539 Addition of APPENDIX E REVISION HISTORY ...

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