APPENDIX D LIST OF CAUTIONS
User’s Manual U16899EJ2V0UD
528
(14/24)
Chapter
Cl
assi
fi
cati
on
Function Details
of
Function
Cautions Page
A/D converter
sampling time
and A/D
conversion start
delay time
The A/D converter sampling time differs depending on the set value of the A/D
converter mode register (ADM).
The delay time exists until actual sampling is started after A/D converter operation
is enabled.
When using a set in which the A/D conversion time must be strictly observed,
care is required for the contents shown in Figure 12-21 and Table 12-3.
p. 265
Chapter 12
Hard
A/D
converter
Register
generating wait
cycle
Do not read data from the ADCR register and do not write data to the ADM, ADS,
PFM, and PFT registers while the CPU is operating on the subsystem clock and
while high-speed system clock oscillation is stopped.
p. 265
If clock supply to serial interface UART0 is not stopped (e.g., in the HALT mode),
normal operation continues. If clock supply to serial interface UART0 is stopped
(e.g., in the STOP mode), each register stops operating, and holds the value
immediately before clock supply was stopped. The TXD0 pin also holds the value
immediately before clock supply was stopped and outputs it. However, the
operation is not guaranteed after clock supply is resumed. Therefore, reset the
circuit so that POWER0 = 0, RXE0 = 0, and TXE0 = 0.
p. 267
Set POWER0 = 1 and then set TXE0 = 1 (transmission) or RXE0 = 1 (reception)
to start communication.
p. 267
UART mode
TXE0 and RXE0 are synchronized by the base clock (f
XCLK0
) set by BRGC0. To
enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks
of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set
within two clocks of base clock, the transmission circuit or reception circuit may
not be initialized.
p. 267
TXS0: Transmit
shift register 0
Do not write the next transmit data to TXS0 before the transmission completion
interrupt signal (INTST0) is generated.
p. 270
At startup, set POWER0 to 1 and then set TXE0 to 1. To stop the operation, clear
TXE0 to 0, and then clear POWER0 to 0.
p. 272
At startup, set POWER0 to 1 and then set RXE0 to 1. To stop the operation,
clear RXE0 to 0, and then clear POWER0 to 0.
p. 272
Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0
pin. If POWER0 is set to 1 and RXE0 is set to 1 while a low level is input,
reception is started.
p. 272
TXE0 and RXE0 are synchronized by the base clock (f
XCLK0
) set by BRGC0. To
enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks
of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set
within two clocks of base clock, the transmission circuit or reception circuit may
not be initialized.
p. 272
Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0
bits.
p. 272
Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always
performed with “number of stop bits = 1”, and therefore, is not affected by the set
value of the SL0 bit.
p. 272
ASIM0:
Asynchronous
serial interface
operation mode
register 0
Be sure to set bit 0 to 1.
p. 272
The operation of the PE0 bit differs depending on the set values of the PS01 and
PS00 bits of asynchronous serial interface operation mode register 0 (ASIM0).
p. 273
Only the first bit of the receive data is checked as the stop bit, regardless of the
number of stop bits.
p. 273
If an overrun error occurs, the next receive data is not written to receive buffer
register 0 (RXB0) but discarded.
p. 273
Chapter 13
Soft
Serial
interface
UART0
ASIS0:
Asynchronous
serial interface
reception error
status register 0
If data is read from ASIS0, a wait cycle is generated. Do not read data from
ASIS0 when the CPU is operating on the subsystem clock and the high-speed
system clock is stopped. For details, see CHAPTER 32 CAUTIONS FOR WAIT.
p. 273
