CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
User’s Manual U16899EJ2V0UD
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11.2 Configuration of Clock Output/Buzzer Output Controller
The clock output/buzzer output controller includes the following hardware.
Table 11-1. Clock Output/Buzzer Output Controller Configuration
Item Configuration
Control registers
Clock output selection register (CKS)
Port mode register 14 (PM14)
Port register 14 (P14)
11.3 Register Controlling Clock Output/Buzzer Output Controller
The following two registers are used to control the clock output/buzzer output controller.
•
Clock output selection register (CKS)
•
Port mode register 14 (PM14)
(1) Clock output selection register (CKS)
This register sets output enable/disable for clock output (PCL) and for the buzzer frequency output (BUZ), and
sets the output clock.
CKS is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CKS to 00H.
