APPENDIX D LIST OF CAUTIONS
User’s Manual U16899EJ2V0UD
520
(6/24)
Chapter
Cl
assi
fi
cati
on
Function Details
of
Function
Cautions Page
Soft
If the TI000 or TI010 pin is high level immediately after system reset, the rising
edge is immediately detected after the rising edge or both the rising and falling
edges are set as the valid edge(s) of the TI000 pin or TI010 pin to enable the
operation of 16-bit timer counter 00 (TM00). Care is therefore required when
pulling up the TI000 or TI010 pin. However, if the TI000 or TI010 pin is high level
when re-enabling operation after the operation has been stopped, the rising edge
is not detected.
p. 150
PRM00:
Prescaler mode
register 00
When the valid edge of the TI010 pin is used, P01 cannot be used as the timer
output pin (TO00). When P01 is used as the TO00 pin, the valid edge of the
TI010 pin cannot be used.
p. 150
Hard
When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the
clock of the Ring-OSC oscillator is divided and supplied as the count clock. If the
count clock is the Ring-OSC clock, the operation of 16-bit timer/event counter 00
is not guaranteed. When an external clock is used and when the Ring-OSC clock
is selected and supplied to the CPU, the operation of 16-bit timer/event counter
00 is not guaranteed, either, because the Ring-OSC clock is supplied as the
sampling clock to eliminate noise.
p. 152
Always set data to PRM01 after stopping the timer operation.
p. 152
If the valid edge of the TI001 pin is to be set for the count clock, do not set the
clear & start mode using the valid edge of the TI001 pin and the capture trigger.
p. 152
Soft
If the TI001 or TI011 pin is high level immediately after system reset, the rising
edge is immediately detected after the rising edge or both the rising and falling
edges are set as the valid edge(s) of the TI001 pin or TI011 pin to enable the
operation of 16-bit timer counter 01 (TM01). Care is therefore required when
pulling up the TI001 or TI011 pin. However, if the TI001 or TI011 pin is high level
when re-enabling operation after the operation has been stopped, the rising edge
is not detected.
p. 152
Hard
PRM01:
Prescaler mode
register 01
When the valid edge of the TI011 pin is used, P06 cannot be used as the timer
output pin (TO01). When P06 is used as the TO01 pin, the valid edge of the
TI011 pin cannot be used.
p. 152
CR01n: 16-bit
timer
capture/compare
register 01n
To change the value of the duty factor (the value of the CR01n register) during
operation, see Caution 2 in Figure 6-20 PPG Output Operation Timing.
p. 156
Values in the following range should be set in CR00n and CR01n:
0000H
≤
CR01n < CR00n
≤
FFFFH
p. 157
CR00n, CR01n:
16-bit timer
capture/compare
registers 00n,
01n
The pulse generated through PPG output has a cycle of [CR00n setting value +
1], and a duty of [(CR01n setting value + 1)/(CR00n setting value + 1)].
p. 157
Chapter 6
Soft
16-bit
timer/
event
counters
00, 01
(TM00,
TM01)
PPG output
In the PPG output operation, change the pulse width (rewrite CR01n) during
TM0n operation using the following procedure.
<1> Disable the timer output inversion operation by match of TM0n and CR01n
(TOC0n4 = 0)
<2> Disable the INTTM01n interrupt (TMMK01n = 1)
<3> Rewrite CR01n
<4> Wait for 1 cycle of the TM0n count clock
<5> Enable the timer output inversion operation by match of TM0n and CR01n
(TOC0n4 = 1)
<6> Clear the interrupt request flag of INTTM01n (TMIF01n = 0)
<7> Enable the INTTM01n interrupt (TMMK01n = 0)
p. 158
