Mindray DC-68, Service Manual

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4-6 Product Principle
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Response to the software control. The software configures DSP_FPGA’s register to complete
the configuration on entire front-end via PCIE interface.
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TR control board. XCVR from DSP_FPGA controls each TR board respectively.
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Scanning generator. It is produced by DSP_FPGA.
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The receiving, pro-processing, uploading of the beam data. XCVR from DSP_FPGA receives
beam data on TR board; logic completes the process and the calculation and sends back to PC
module via PGIE. Logic algorithm of the pro-processing can be upgraded.

Clock distribution includes front-end clock and XGVR reference clock. The clock source and
distribution circuit is available inside the board. Distribute DSP_FPGA and each TR board.
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RATE distribution. RATE, a special clock, routes around with front-end clock and distributes to
DSP_FPGA and each TR board.
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ATGC distribution. Distribute ATGC’s differential voltage to each TR board.
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Probe management. DSP_FPGA completes the probe management via SPI controlling CPLD
on control probe board. CPLD online upgrade.
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The pencil probe is in the place and has the access to the ID.ID signal refers to one wire signal.
The specialized buffer is needed.
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Supports the physiological signal module and provides the serial.
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Distributes JTAG chain facing forwards the front-end.
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Provides 4D’s control and driving as the carrier of 4D&TEE board.
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Test signal of output acoustic power.
4.2.5 4D Module
The generator inside 4D probe requires the driving signal. With the specialized requirements of the
voltage and the phase of the driving signal, the driving circuit comes into form.
Temperature signal test on TEE probe needs balance bridge current and ADC sampling.
The two probes are both optional. The related circuit has an independent module. The supportive
circuits of the two probe bound together come into 4D&TEE module and are placed above the
engine board.
HALL digital signal from 4D probe shows the location of the probe. The signal does not arrive at
4D&TEE module, but goes into DSP_FPGA directly.