Maxim Integrated MAX32660 User Manual Download Page 75

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MAX32660 User Guide

Maxim Integrated

Page 75 of 195

To configure a channel for buffer chaining, initialize the following registers:

•

•

•

•

•

•

•

When the

.rlden

bit must not be set. In addition, any writes to the

DMAn_CFG

.chen

and

DMAn_CFG

.rlden

bits. After all registers are

initialized, the last operation involves writing to the

DMAn_CFG

.chen

and

DMAn_CFG

.rlden

bits. This starts the DMA.

Set the

DMAn_CFG

.ctzien

bit in the register to receive an interrupt after each buffer is accessed. In addition, set the

DMAn_CFG

.chdien

bit to provide an interrupt in case of a bus error.

Caution

: Setting the

DMAn_CFG

.chen and the

DMAn_CFG

.rlden bits separately risks a race condition. The condition occurs

between a DMA completion interrupt service routine initializing the reload registers for the third buffer before the software
initialization of these registers for the second buffer.

When the first DMA transfer completes (based on the

DMAn_CNT

.cnt

bit value), a CTZ interrupt occurs, and the

DMAn_SRC

DMAn_DST

, and

DMAn_CNT

registers are reloaded from the corresponding reload registers.

The

DMAn_STAT

.ch_st =

1 indicating

that the DMA is now busy with the second DMA transfer defined in the reload registers. If

DMAn_STAT

.ch_st =

0, then the

initial and second DMA transfers have completed. If there are additional buffers to chain, the interrupt service routine
initializes the

DMAn_SRC_RLD

DMAn_DST_RLD

, and

DMAn_CNT_RLD

registers and sets the

DMAn_CNT_RLD

.rlden

bit. The

interrupt service routine does not write to the

, and

registers, just the

reload registers.

To prevent improper operation, program the address bits before setting the

DMAn_CFG

.chen

and

DMAn_CNT_RLD

.rlden

bits.

7.8

DMA Interrupts

Enable interrupts for each channel by setting

DMA_INT_EN

.chien.

When an interrupt is pending, the corresponding

DMA_INT_FL

.ipend =

1. The

DMA_INT_FL

.ipend

field is read-only, to clear the interrupt use the

DMAn_STAT

write a 1 to the field that indicates the cause of the interrupt.

A channel interrupt (

DMAn_STAT

ipend =

1) is caused by:

DMAn_CFG

.ctzien

= 1

If enabled, all CTZ occurrences set the

DMAn_STAT

ipend

bit.

DMAn_CFG

.chdien

= 1

If enabled, any clearing of the

DMAn_STAT

.ch_st

bit sets the

DMAn_STAT

.ipend

bit. Examine the

DMAn_STAT

DMAn_CFG

.chdien

bit also enables the

DMAn_STAT

.to_st

bit. The

DMAn_STAT

.to_st

bit does not clear the

DMAn_STAT

.ch_st

bit.

To clear the channel interrupt, write 1 to the cause of the interrupt (the

.ctz_st,

.rld_st,

.bus_err,

.to_st

bits).

Summary of Contents for MAX32660

Page 1: ...ser guide provides application developers information on how to use the memory and peripherals of the MAX32660 microcontroller Detailed information for all registers and fields in the device are cover...

Page 2: ...MAX32660 User Guide Maxim Integrated Page 2 of 195 Table of Contents 1 Introduction 13 2 Overview 13 3 Memory Register Mapping and Access 15 4 System Clocks Reset and Power Management 21...

Page 3: ...MAX32660 User Guide Maxim Integrated Page 3 of 195 5 Flash Controller 51 6 General Purpose I O and Alternate Function Pins 58 7 DMA Controller 71...

Page 4: ...MAX32660 User Guide Maxim Integrated Page 4 of 195 8 UART 84 9 Real Time Clock RTC 96 10 Timers 105...

Page 5: ...MAX32660 User Guide Maxim Integrated Page 5 of 195 11 Watchdog Timer WDT 126 12 I2 C Master Slave Serial Controller 131...

Page 6: ...MAX32660 User Guide Maxim Integrated Page 6 of 195 13 Serial Peripheral Interface 0 SPI0 159 14 SPIMSS SPI1 I2 S 178...

Page 7: ...MAX32660 User Guide Maxim Integrated Page 7 of 195 15 Trademarks 195 16 Revision History 195...

Page 8: ...Devices and the Direction the I2 C Signals 132 Figure 12 2 I2 C Write Data Transfer 134 Figure 12 3 I2 C Specification Minimum and Maximum Clock Parameters for Standard and Fast Mode 136 Figure 12 4 I...

Page 9: ...ster 42 Table 4 21 Reset Register 1 43 Table 4 22 Peripheral Clock Disable Register 1 43 Table 4 23 Event Enable Register 44 Table 4 24 Revision Register 44 Table 4 25 System Status Interrupt Enable R...

Page 10: ...able 6 23 GPIO Drive Strength 0 Select Register 68 Table 6 24 GPIO Drive Strength 1 Select Register 69 Table 6 25 GPIO Pullup Pulldown Select Register 70 Table 7 1 DMA Channel Registers 71 Table 7 2 C...

Page 11: ...Registers 129 Table 11 3 Watchdog Timer Control Register 129 Table 11 4 Watchdog Timer Reset Register 130 Table 12 1 I2 C Bus Terminology 131 Table 12 2 I2 C Address Byte Format 138 Table 12 3 I2 C R...

Page 12: ...Interrupt Flag Registers 174 Table 13 14 SPI Interrupt Enable Registers 176 Table 13 15 SPI Wakeup Status Flags Registers 177 Table 13 16 SPI Wakeup Enable Registers 177 Table 13 17 SPI Status Registe...

Page 13: ...M4 with FPU Floating Point Unit The device enables designs with complex sensor processing without compromising battery life It also offers legacy designs an easy and cost optimal upgrade path from 8 o...

Page 14: ...MAX32660 User Guide Maxim Integrated Page 14 of 195 Figure 2 1 MAX32660 High Level Block Diagram...

Page 15: ...is most typically accessed in 32 bit 4 byte units It may also be accessed depending on the implementation in 8 bit 1 byte or 16 bit 2 byte widths The total range of the memory space is 32 bits in wid...

Page 16: ...maximum Two different standard core bus masters are used by the Arm Cortex M4 core and the Arm debugger to access this memory area The I Code AHB bus master is used for instruction decode fetching fro...

Page 17: ...ea by other non Arm core bus masters such as the Standard DMA AHB bus master will not trigger a bit banding operation and will instead result in an AHB bus error The SRAM area on the MAX32660 is capab...

Page 18: ...execution mode as opposed to the standard user thread execution mode This helps ensure that critical system settings controlled in this area are not altered inadvertently or by errant code that shoul...

Page 19: ...d peripheral and memory areas are also accessed using this bus master 3 3 6 AHB Master 3 3 6 1 Standard DMA The Standard DMA bus master has access to all off core memory areas accessible by the System...

Page 20: ...I2C0_ 0x4001 D000 0x4001 DFFF I2C 1 I2C1_ 0x4001 E000 0x4001 EFFF Standard DMA DMA_ 0x4002 8000 0x4002 8FFF Flash Controller FLC_ 0x4002 9000 0x4002 93FF Internal Cache Controller ICC_ 0x4002 A000 0x...

Page 21: ...ait states for the internal flash memory Changing the core operating voltage immediately reduces the output frequency of the High Frequency Internal Oscillator as shown in Table 4 1 below When operati...

Page 22: ...e number of Flash Wait States per Table 4 2 below a Set GCR_MEM_CTRL fws to the minimum value shown for the selected OVR and System Clock 8 Perform a Peripheral Reset a Set GCR_RST0 periph_rst 1 On ea...

Page 23: ...system clock frequency prior to changing the system oscillator prescaler Table 4 2 Minimum Flash Wait State Setting for Each OVR Setting fSYSCLK fHFIO Core Operating Voltage Range Setting Core Voltag...

Page 24: ...sources High Frequency Internal Oscillator HFIO 8kHz Internal Ultra Low Power Nano Ring Oscillator 32 768kHz External Crystal Oscillator The selected SYSOSC is the input to the system oscillator presc...

Page 25: ...oft Peripheral System Oscillator GCR_CLK_CTRL clksel 0 HFIO 0 HFIO 0 HFIO Retains State Retains State System Clock Prescaler GCR_CLK_CTRL psc 1 1 1 Retains State Retains State 4 3 Oscillator Sources a...

Page 26: ...alarm can wake this device from SLEEP or DEEPSLEEP mode if the GCR_PM rtcwk_en is set to 1 and the RTC alarm is configured The 32kHz oscillator is disabled by hardware by a Power On Reset All other fo...

Page 27: ...egisters memory and peripherals are enabled The CPU is running and executing application code All oscillators are available for application use if enabled Dynamic clocking allows firmware to selective...

Page 28: ...d during BACKUP mode The Arm Cortex M4 with FPU state and all system and peripheral registers do not retain state The RTC and AoD registers do retain state during BACKUP mode RAM retention in BACKUP m...

Page 29: ...trol Registers GCR including the clock configuration are unaffected Initiate a Peripheral Reset by setting GCR_RST0 periph_rst to 1 4 7 2 Soft Reset This is the same as a Peripheral Reset except that...

Page 30: ...irmware On Enabled by hardware Cannot be disabled Off Disabled by hardware Cannot be enabled Auto Off Can either be left on or automatically gated off when in this power mode No Effect N A Not Applica...

Page 31: ...gister 0x0004 ICC0_MEM_SIZE R0 Cache Memory Size Register 0x0100 ICC0_CACHE_CTRL R W Cache Control Register 0x0700 ICC0_INVALIDATE R W Cache Invalidate Register 4 9 1 ICC0 Register Details Table 4 8 I...

Page 32: ...1 Enable Cache Table 4 11 ICC Invalidate Register ICC Invalidate Register ICC0_INVALIDATE 0x0700 Bits Name Access Reset Description 31 0 WO Invalidate Any write to this register of any value invalida...

Page 33: ...Refer to Table 3 1 APB Peripheral Base Address Map for the addresses of all APB mapped peripherals The Global Control Registers are only reset on a System Reset Watchdog Timer Reset and a Power On Re...

Page 34: ...is bit is controlled by hardware Firmware should not change the state of this bit during normal operation Any change to this bit flushes the instruction cache and the data cache 0 Physical layout matc...

Page 35: ...e Do not modify this field 14 spi1 R W1O 0 SPIMSS SPI1 I2S Reset Write 1 to reset the peripheral state to the reset default state When complete this field will read 0 0 SPIMSS SPI1 I2S peripheral not...

Page 36: ...ld will read 0 0 WDT0 peripheral not in reset 1 Write 1 to reset the WDT0 peripheral 0 dma R W1O 0 Standard DMA Reset Write 1 to reset the peripheral state to the reset default state When complete thi...

Page 37: ...ble the 32kHz oscillator 16 14 RO Reserved for Future Use Do not modify this field 13 clkrdy R W 0 System Oscillator Clock Source Ready When the System Oscillator source is modified by changing the GC...

Page 38: ...to exit all low power modes and transition directly to ACTIVE mode Refer to section 9 2 3 RTC Wakeup From DEEPSLEEP BACKUP Power Modes for details on enabling the RTC as a wakeup source 0 Wakeup from...

Page 39: ...clock to the peripheral does not affect the p riph ral s r gist rs Write 1 to disable set to 0 to enable 0 Peripheral Enabled 1 Peripheral Disabled 15 timer0d R W 0 Timer0 Clock Disable Setting this...

Page 40: ...his field disables the APB clock to this peripheral When the clock is disabled the peripheral power consumption is reduced and the peripheral is disabled Disabling the cl ck t th p riph ral s n t aff...

Page 41: ...the RAM and reset the RAM contents use the register PWRSEQ_LPMEMSD Low Power Mode RAM Shut Down Control 10 ram2_ls 0 System RAM 2 Data Retention Enable Set this field to 1 to enable Light Sleep mode...

Page 42: ...Wait States for additional information 0 Reserved for Future Use 1 1 Wait State 1 System Clock 2 2 Wait States 3 3 Wait States 4 4 Wait States Minimum value for HFIO System Clock 96MHz 5 5 Wait States...

Page 43: ...s Name Access Reset Description 31 12 R W 0 Reserved for Future Use Do not modify this field 11 iccd R W 0 ICC Clock Disable Setting this field disables the APB clock to this peripheral When the clock...

Page 44: ...tion 31 16 RO Reserved for Future Use Do not modify this field 15 0 revision RO N A Maxim Integrated Chip Revision This field reads the chip revision id A1 ascii encoded visi n 1 0x4131 Table 4 25 Sys...

Page 45: ...ration Valid Note If this field reads 0 the device configuration is invalid and a device error has occurred Please contact Maxim Integrated technical support for additional assistance Table 4 28 Syste...

Page 46: ...sters and peripherals in that power domain are reset This improves reliability and safety by guarding against a low voltage condition corrupting the contents of the registers and the device state Disa...

Page 47: ...ally disable the LDO 0 LDO Enabled 1 LDO Disabled Default after a POR 15 13 R W 0 Reserved for Future Use Do not modify this field 12 vcore_por_dis R W 1 VCORE POR Disable for DEEPSLEEP and BACKUP Mod...

Page 48: ...ng voltage and the frequency of the internal high frequency internal oscillator On Power On Reset this field defaults to 1 1V output 10 with the fINT_CLK 96MHz Note If VCORE is connected to an externa...

Page 49: ...To enable the device to wake up from a low power mode on a GPIO pin transition first set the GCR_PM GPIO wakeup enable field to 1 GCR_PM gpiowk_en 1 Table 4 34 Low Power Wakeup Enable for GPIO0 Regis...

Page 50: ...range 0 System RAM 2 Powered On Enabled 1 System RAM 2 Powered Off Disabled 1 sram1_off R W 0 System RAM 1 0x2000 3FFF 0x2000 7FFF Shut Down Write 1 to shut down power to System RAM 1 memory range 0...

Page 51: ...ernal flash memory is mapped with a start address of 0x0000 0000 and an end address of 0x0003 FFFF for a total of 256KB Table 5 1 Internal Flash Memory Organization Page Number Size in Bytes Start Add...

Page 52: ...l flag FLC_INTR access_fail to indicate an access violation occurred 5 3 3 Flash Write Width The Flash Controller supports write widths of either 32 bits or 128 bits Selection of the flash write width...

Page 53: ...re set 5 3 5 Page Erase Perform the following to erase a page of internal flash memory 1 If desired enable Flash Controller interrupts by setting the FLC_INTR access_fail_ie and FLC_INTR done_ie bits...

Page 54: ...s generated FLC_INTR access_fail 1 5 4 Flash Controller Registers The FLC base peripheral address is 0x4002 9000 Refer to Table 3 1 APB Peripheral Base Address Map for the addresses of all APB mapped...

Page 55: ...oltage Range Selection for detailed usage information on this setting 0 Low voltage operation disabled Default 1 Low voltage operation enabled Note The PWRSEQ_LP_CTRL ovr field must be set to 0b00 pri...

Page 56: ...clears this bit when the mass erase operation completes 0 No operation 1 Initiate mass erase Note This field is protected and cannot be set to 0 by application code 0 write R W1O 0 Write If this field...

Page 57: ...es 0 Operation not complete or not in process 1 Flash operation complete Table 5 6 Flash Controller Data Register 0 Flash Controller Data Register 0 FLC_DATA0 0x30 Bits Name Access Reset Description 3...

Page 58: ...and configured as a level triggered interrupt a rising edge falling edge or both rising and falling edge interrupt All GPIO share the same interrupt vector No all GPIO are available on all packages Th...

Page 59: ...1 GPIO0 2 3 P0 2 I2C1_SCL SPI1_SCK I2S_BCLK 1 2 32KCAL GPIO0 3 3 P0 3 I2C1_SDA SPI1_SS0 I2S_LRCLK 1 2 TMR0 GPIO0 4 P0 4 SPI0_MISO UART0_TX GPIO0 5 P0 5 SPI0_MOSI UART0_RX GPIO0 6 P0 6 SPI0_SCK UART0_C...

Page 60: ...IO0_AF0_SEL pin 1 b GPIO0_AF1_SEL pin 0 2 Configure the pin for pull up pull down or high impedance mode Refer to GPIO_PULL_SEL register for pull up and pull down selection 3 GPIO pins with I2 C as an...

Page 61: ...ers 6 3 Alternate Function Configuration Table 6 5 below shows the alternate function selection matrix Write the GPIO0_AF0_SEL and GPIO0_AF1_SEL fields as shown in the table to select the desired alte...

Page 62: ...details on configuring a pin for I O mode Table 6 6 GPIO Port Interrupt Vector Mapping GPIO Interrupt Source GPIO Interrupt Flag Register Device Specific Interrupt Vector Number GPIO Interrupt Vector...

Page 63: ...ption 0x0000 GPIO0_AF0_SEL R W I O and Alternate Function 1 Select Register 0x000C GPIO0_OUT_EN R W Output Enable Register 0x0018 GPIO0_OUT R W Output Register 0x0024 GPIO0_IN RO Input Register 0x0028...

Page 64: ...eld 13 2 R W 0 GPIO Output Enable Setting a bit to 1 enables the output driver for the respective pin 0 Output mode disabled output driver disabled 1 Output mode enabled output driver enabled 1 R W 1...

Page 65: ...sponding GPIO pin 1 Edge triggered interrupt for corresponding GPIO pin Note This bit has no effect unless the corresponding bit in the GPIO0_INT_EN register is set Table 6 14 GPIO Port Interrupt Pola...

Page 66: ...to clear the interrupt pending status flag Table 6 17 GPIO Wakeup Enable Registers GPIO Wakeup Enable Register GPIO0_WAKE_EN 0x004C Bits Name Access Reset Description 31 14 R W 0 Reserved for Future...

Page 67: ...GPIO_PULL_SEL register is set to 1 Table 6 20 GPIO Alternate Function Select Register GPIO Alternate Function Select Register GPIO0_AF1_SEL 0x0068 Bits Name Access Reset Description 31 14 R W 0 Reserv...

Page 68: ...for the respective I O pin 0 Fast slew rate selected 1 Slow slew rate selected Note Refer to the MAX32660 datasheet for detailed electrical characteristics of the fast and slow slew rates Table 6 23 G...

Page 69: ...h section above for the selection options on these I O pins Refer to the symbols VOL_GPIO and VOH_GPIO in the MAX32660 Data Sheet Electrical Characteristics table for details of the drive strengths fo...

Page 70: ...I O pins 9 8 R W 0 Pulldown Resistor Select This bit should always be set to 0 The I O pins with I2C as an alternate function only a weak pull down resistor 0 Pull down resistor selected 1 Invalid Re...

Page 71: ...omponents Figure 7 1 DMAC Block Diagram All direct memory access DMA transactions consist of an advanced high performance bus AHB burst read from the source into the DMA FIFO followed by an AHB burst...

Page 72: ...y cleared under the following conditions Bus error cleared immediately CTZ when the DMAn_CFG rlden 0 cleared at the end of the AHB R W burst DMAn_STAT chen bit transitions to 0 cleared at the end of t...

Page 73: ...is set using the DMAn_DST register and is incremented automatically if DMAn_CFG dstinc is set to 1 Table 7 3 Source and Destination Address Definition DMAn_CFG reqsel Transfer Source Address Register...

Page 74: ...width This determines the maximum data width used during each write of the AHB burst one byte two bytes or four bytes dstinc Destination increment enable Increments DMAn_DST 7 6 Count To Zero CTZ Cond...

Page 75: ...this case DMAn_STAT ch_st 1 indicating that the DMA is now busy with the second DMA transfer defined in the reload registers If DMAn_STAT ch_st 0 then the initial and second DMA transfers have complet...

Page 76: ...he DMAn_CFG r gist r t c ntr l ach chann l s 10 bit timer Scale the input clock for the timer using the DMAn_CFG pssel field The options available are fHCLK 256 fHCLK 64K fHCLK 16M Note HCLK is the AH...

Page 77: ...ority to channels executing memory to memory transfers to prevent starvation of other DMA channels 7 13 Standard DMA Control Registers The DMA base peripheral address is 0x4002 8000 Refer to Table 3 1...

Page 78: ...example th a r ss f r hann l 3 s 3_ _ L r gist r is hann l 3 as Address 0x4002 0160 plus the offset of the DMAn_DST_RLD register 0x0018 which gives the address 0x4002 0178 for DMA3_DST_RLD Table 7 9 S...

Page 79: ...000 1 byte 0b00001 2 bytes 0b00010 3 bytes 0b11111 32 bytes 23 RO 0 Reserved for Future Use Do not modify this field 22 distinc R W 0 Destination Increment Enable This bit enables the automatic increm...

Page 80: ...ated for this channel 000 3 4 001 7 8 010 15 16 011 31 32 100 63 64 101 127 128 110 255 256 111 511 512 10 reqwait R W 0 Request Wait Enable When enabled delay the timeout timer start until after the...

Page 81: ...urred 1 Reload event occurred 2 ctz_st R W1C 0 CTZ Status This bit is set by hardware when a Count to zero CTZ has occurred if enabled Write 1 to clear 0 CTZ has not occurred 1 CTZ has occurred 1 ipen...

Page 82: ...ransfers the actual address field is either ignored or forced to zero because peripherals only have one location to read write data based on the request select chosen If DMAn_CFG dstinc 1 then this re...

Page 83: ...estination Address Reload Value If DMAn_CFG rlden 1 then the value of this register is loaded into DMAn_DST upon a CTZ condition Table 7 18 DMA Count Reload Register DMA Count Reload Register DMAn_CNT...

Page 84: ...d CTS Null modem support Break generation and detection Wakeup from DEEPSLEEP on UART edge with no character loss RX Timeout detection 8 2 UART Frame Characters Character sizes of 5 to 8 bits are supp...

Page 85: ...not received a character for a set time First and Last BREAK characters 8 4 UART Bit Rate Calculation The UART peripheral clock is used as the input clock to the UART bit rate generator The following...

Page 86: ...the DMA Configuration Register UARTn_DMA The RX FIFO DMA channel and TX FIFO DMA channels operate independently and each can be enabled or disabled individually Enable the RX FIFO DMA channel by sett...

Page 87: ...RT is receiving data and the RX FIFO reaches the level set in the 6 bit register field UARTn_CTRL1 rts_fifo_lvl then the RTS signal of this UART is deasserted informing the transmitting UART to stop s...

Page 88: ...Modem Support 0 Normal operation for RTS CTS and TXD RXD 1 Null Modem Mode RTS CTS swapped TXD RXD swapped 12 flowpol R W 0 RTS CTS Polarity 0 RTS CTS asserted is 0 1 RTS CTS asserted is 1 11 flow R W...

Page 89: ...it rate generator is off 1 UART Enabled bit rate generator is active Table 8 4 UART Control 1 Register UART Control 1 Register UARTn_CTRL1 0x0004 Bits Name Access Reset Description 31 22 0 R W 0 Reser...

Page 90: ...e condition occurs and is automatically cleared when the condition is no longer valid 0 TX FIFO is not full 1 TX FIFO is full 6 tx_empty RO 1 TX FIFO Empty Flag This field reads 1 when the TX FIFO is...

Page 91: ...for the first BREAK received on the UART 0 Interrupt disabled 1 Interrupt enabled 6 tx_fifo_lvl R W 0 TX FIFO Threshold Level Interrupt Enable Set this field to 1 to enable an interrupt when the numbe...

Page 92: ...e UART receives a series of BREAK frames this flag is set when the first BREAK frame is received Write 1 to clear this field 6 tx_fifo_lvl R W1C 0 Transmit FIFO Threshold Interrupt Flag This interrupt...

Page 93: ...curs while receiving data Write 1 to clear Table 8 8 UART Rate Integer Register UART Baud Rate Integer Register UARTn_BAUD0 0x0014 Bits Name Access Reset Description 31 17 R W 0 Reserved for Future Us...

Page 94: ...Level DMA Trigger If the RX FIFO level is greater than this value the DMA channel transfers data from the RX FIFO into memory DMA transfers continue until the RX FIFO is empty To avoid an RX FIFO over...

Page 95: ...IFO 0x0024 Bits Name Access Reset Description 7 0 data RO 0 TX FIFO Data Output Peek Register Reads from this register return the next character available for transmission at the end of the TX FIFO If...

Page 96: ...n each rollover of the RTC_SSEC rtss field Together the 40 bits represent time in seconds up to approximately 136 years A programmable time of day alarm is usable with the 32 bit seconds counter to pr...

Page 97: ...e RTC provides time of day and sub second interval alarm functions The time of day alarm is implemented by matching the count values in the counter register with the value stored in the alarm register...

Page 98: ...ond alarm allowing a maximum interval of 16 777 216 seconds with a resolution of approximately 3 9 msec You must disable the sub second interval alarm RTC_CTRL alarm_ss_en prior to changing the interv...

Page 99: ...any time and the bit remains clear until set by hardware when the next ripple occurs A separate Ready Enable RTC_CTRL ready_int_en bit is provided to generate an interrupt when hardware sets the RTC_...

Page 100: ...RTC_CTRL 32kout_en to 1 enabling the square wave output on the 32KCAL alternate pin function 4 Measure the square wave output and compare it to an accurate reference clock 5 Set RTC_CTRL write_en to 1...

Page 101: ...nterrupt is generated Table 9 5 RTC Sub Second Alarm Register RTC Sub Second Alarm Register RTC_RSSA 0x0C Bits Name Access Reset Description 31 0 rssa R W 0 Sub second Alarm Sets the starting value fo...

Page 102: ...nction pin with the frequency determined by the RTC_CTRL freq_sel field Note This bit is set to 0 on a POR and is not affected by other resets 7 alarm_ss_fl R W 0 Sub second Alarm Interrupt Flag This...

Page 103: ...CTRL write_en After writing to this bit check the RTC_CTRL busy flag for 0 to determine when the RTC synchronization is complete 0 RTC disabled 1 RTC enabled Table 9 7 RTC Trim Register RTC Trim Regis...

Page 104: ...ld is only reset on POR and not effected by other forms of reset 2 hyst_en R W 0 RTC Oscillator Hysteresis Buffer Enable Enables the RTC hysteresis buffer in noise immunity mode This increases DC curr...

Page 105: ...either the timer clock an external stimulus on the timer pin or a combination of both The TMRn_CNT register is always readable even while the timer is enabled and counting Each timer mode has a user c...

Page 106: ...GPIO Timer pin assignments are detailed in the data sheet for the specific device When the timer pin alternate function is enabled the timer pin will have the same electrical characteristics such as...

Page 107: ...ETO TMR_CNT BEFORE THE TIMER IS ENABLED THE DEFAULT VALUE OF TMR_CNT FOR THE FIRST PERIOD AFTER A SYSTEM RESET IS 0X0000_0000 UNLESS CHANGED BY SOFTWARE TMR_CN TPL 1 TMR_CN TPL 0 TIMER PIN OUTPUT 0X00...

Page 108: ...re the pin as a timer output and configure the electrical characteristics as needed b Set TMRn_CN tpol to match the desired inactive state 5 If using the timer interrupt enable the interrupt and set t...

Page 109: ...AN WRITE ANY INITIAL VALUETO TMR_CNT BEFORE THE TIMER IS ENABLED THE DEFAULT VALUE OF TMR_CNT FOR THE FIRST PERIOD AFTER A SYSTEM RESET IS 0X0000_0000 UNLESS CHANGED BY SOFTWARE SOFTWARE CLEARS BIT TM...

Page 110: ...onfigure the pin as a timer output and configure the electrical characteristics as needed b Set TMRn_CN tpol to match the desired inactive state 5 If using the timer interrupt enable the interrupt and...

Page 111: ...MR_CN TEN TMR_CNT 0X0000_0000 0X0000_0001 TMR_INT IRQ TMR_CN CMP TMR_CNT AUTOMATICALLY RELOADS WITH 0X0000_0001 AT THE END OF THE TIMER PERIOD BUT SOFTWARE CAN WRITE ANY INITIAL VALUETO TMR_CNT BEFORE...

Page 112: ...b Set TMRn_CN tpol to match the desired initial inactive state 4 If using the timer interrupt enable the interrupt and set the interrupt priority 5 Write an initial value to TMRn_CNT if desired This...

Page 113: ...value reaches the TMRn_CMP value resulting in the timer output signal transitioning high and the TMRn_CNT value resetting to 0x0000 0001 10 7 2 PWM Mode Configuration Complete the following steps to...

Page 114: ...CN tpol is 0 the ratio of the PWM output high time to the total period is calculated using the following equation _ _ _ 100 If TMRn_CN tpol is set to 1 the ratio of the PWM output high time to the tot...

Page 115: ...TH 0X0000_0001 AFTER A CAPTURE EVENT OR WHEN TMR_CNT TMR_CMP BUT SOFTWARE CAN WRITE ANY INITIAL VALUE TO TMR_CNT BEFORE THE TIMER IS ENABLED THE DEFAULT VALUE OF TMR_CNT FOR THE FIRST PERIOD AFTER A S...

Page 116: ...b 3 Set TMRn_CN pres3 TMRn_CN pres to set the prescaler that determines the timer frequency 4 If using the timer pin a Configure the pin as a timer output and configure the electrical characteristics...

Page 117: ...HE TIMER PERIOD BUT SOFTWARE CAN WRITE ANY INITIAL VALUETO TMR_CNT BEFORE THE TIMER IS ENABLED THE DEFAULT VALUE OF TMR_CNT FOR THE FIRST PERIOD AFTER A SYSTEM RESET IS 0X0000_0000 UNLESS CHANGED BY S...

Page 118: ...in as a timer output and configure the electrical characteristics as needed b Set TMRn_CN tpol to match the desired inactive state 5 If using the timer interrupt enable the interrupt and set the inter...

Page 119: ...RITE ANY INITIAL VALUETO TMR_CNT BEFORE THE TIMER IS ENABLED THE DEFAULT VALUE OF TMR_CNT FOR THE FIRST PERIOD AFTER A SYSTEM RESET IS 0X0000_0000 UNLESS CHANGED BY SOFTWARE TMR_CN TPL 1 TMR_CN TPL 0...

Page 120: ...imer frequency 4 Configure the timer pin a Configure the pin as a timer input and configure the electrical characteristics as needed b Set TMRn_CN tpol to match the desired initial inactive state 5 If...

Page 121: ...inues incrementing 3 The timer interrupt bit TMRn_INT irq is set A Timer IRQ is generated if enabled 4 If the end of the timer period was caused by a transition on the timer pin a TMRn_CNT is reset to...

Page 122: ...er Name Access Description 0x0000 TMRn_CNT R W Timer Counter Register 0x0004 TMRn_CMP R W Timer Compare Register 0x0008 TMRn_PWM R W Timer PWM Register 0x000C TMRn_INT R W Timer Interrupt Register 0x0...

Page 123: ...r Capture Compare event occurs Table 10 5 Timer Interrupt Registers Timer Interrupt Register TMRn_INT 0x000C Bits Name Access Reset Description 31 1 R 0 Reserved for Future Use Do not modify this fiel...

Page 124: ...n s cti n f r tp l usag an meaning 5 3 pres R W 0 Timer Prescaler Select ts th tim r s pr scal r valu h pr scal r ivi s th P LK input t th tim r an s ts th tim r s c unt cl ck _ h tim r s pr scal r s...

Page 125: ...ontrol Register TMRn_CN 0x0010 Bits Name Access Reset Description 2 0 tmode R W 0 Timer Mode Select ts th tim r s p rating m tmode Selected Timer Mode 000b One Shot 001b Continuous 010b Counter 011b P...

Page 126: ...counter within the interrupt time period WDT0_CTRL int_period the watchdog timer generates a watchdog timer interrupt If the watchdog timer reset is enabled and the software does not reset the counter...

Page 127: ...m execution error and take whatever steps necessary to guard against a software corruption issue 11 3 Interrupt and Reset Period Timeout Configuration Each watchdog timer supports two independent time...

Page 128: ...Disable Setting WDT0_CTRL wdt_en to 0 disables the watchdog timer 11 5 2 Automatic Disable A power on reset POR event automatically disables the watchdog timers by setting WDT0_CTRL wdt_en to 0 Note...

Page 129: ...30 12 RO 0 Reserved for Future Use Do not modify this field 11 rst_en R W 0 Reset Enable Enable Disable system reset if the WDT0_CTRL rst_period expires Only reset by power on reset 0 Disabled 1 Enabl...

Page 130: ...until a watchdog timer interrupt is generated 0xF 216 0xE 217 0xD 218 0xC 219 0xB 220 0xA 221 0x9 222 0x8 223 0x7 224 0x6 225 0x5 226 0x4 227 0x3 228 0x2 229 0x1 230 0x0 231 Table 11 4 Watchdog Timer...

Page 131: ...an I2 C master device addresses it For detailed information on I2 C bus operation refer to Maxim Application Note 4024 SPI I C Bus Lines Control Multiple Peripherals 12 1 1 Related Documentation For...

Page 132: ...upports I2 C Standard Mode Fast Mode Fast Mode Plus and High Speed Hs mode Data transfer rates up to 100 kbps in Standard Mode 400 kbps in Fast Mode 1 Mbps in Fast Mode Plus 3 4 Mbps in Hs Mode Multi...

Page 133: ...and a STOP condition occurs when a bus master allows SDA to be pulled from low to high while SCL is high Because these are unique conditions that cannot occur during normal data transfer they are use...

Page 134: ...ithout an intervening STOP condition to start a new transfer A receiver can generate a NACK after a byte transfer if any of the following conditions occur No receiver is present on the bus with the tr...

Page 135: ...avoid the need for any pull up resistor This should only be used in systems where no I2 C slave device can hold the SCL line low Push pull operation is enabled by setting I2Cn_CTRL0 sclppm to 1 SDA al...

Page 136: ...er slave has one 8 byte deep transmit FIFO TX FIFO and one 8 byte deep receive FIFO RX FIFO that reduces processor overhead To further speed transfers the DMA can read and write to each FIFO When the...

Page 137: ...mit operation as either master or slave when the TX FIFO is empty after the last byte is shifted out SCL is automatically held low until data is written to the TX FIFO Master transmitters can stop clo...

Page 138: ...r sends is the 10 bit Slave Addressing byte which includes the first two bits of the 10 bit address followed by a 0 for the R W bit The master then sends a second byte representing the remainder of th...

Page 139: ...data is not unintentionally transmitted In addition the Transmit Lockout Flag is set I2Cn_INTFL0 txloi 1 and writes to the TX FIFO are ignored until firmware acknowledges the external event by cleari...

Page 140: ...the TX FIFO I2Cn_TXCTRL0 txth and RX FIFO I2Cn_RXCTRL0 rxth threshold levels 12 9 1 I2C Transmit DMA Burst Size When the TX FIFO byte count I2Cn_TXCTRL1 txfifo is less than or equal to the TX FIFO Thr...

Page 141: ...dition The master can also generate a STOP condition by setting I2Cn_MSTR_MODE stop 1 If both START and RESTART conditions are enabled at the same time a START condition is generated first Then at the...

Page 142: ...s for the desired I2 C operating frequency The I2 C peripheral clock is supplied directly by the system peripheral clock fPCLK The SCL high time is configured in the I2 C Clock High Time register fiel...

Page 143: ...rrors in the calculation by rounding up the I2Cn_HS_CLK hs_clk_hi result if the least significant bit is set 12 14 TX FIFO Preloading There may be situations where when operating as a slave firmware w...

Page 144: ...troller from the TX FIFO 5 The I2 C controller receives an ACK from the slave and the controller sets address ACK field I2Cn_INTFL0 adracki 1 6 The I2 C controller receives data from the slave and aut...

Page 145: ...pin This field should not be set unless any external slave device will never actively drive SCL low 0 SCL operates in standard I2C open drain mode 1 SCL operates in push pull mode without the need for...

Page 146: ...ion 0 Respond to IRM with ACK 1 Respond to IRM with NACK 3 irxm R W 0 Interactive Receive Mode IRXM When receiving data allows for an Interactive Receive Mode IRM interrupt event after each received b...

Page 147: ...lave 11 Receive data Master or Slave 12 Transmit data ACK Master or Slave 13 NACK stage Master or Slave 14 Reserved for Future Use 15 Another master is addressing another slave The transaction is ongo...

Page 148: ...expected sequence Write 1 to clear this field Writing 0 has no effect 0 Error condition has not occurred 1 Out of sequence START condition occurred 12 dnreri R W1C 0 Slave Mode Do Not Respond Interrup...

Page 149: ...r bytes Default 4 rxthi RO 1 RX FIFO Threshold Level Interrupt Flag This field is set by hardware if the number of bytes in the Receive FIFO is greater than or equal top the Receive FIFO threshold lev...

Page 150: ...NACK from Slave Interrupt Enable Set this field to enable events for Master Mode external device data NACK events 0 Interrupt disabled 1 Interrupt enabled 10 adrerie R W 0 Master Mode Received Address...

Page 151: ...12 8 I2 C Interrupt Status Flags 1 Registers I2C Interrupt Status Flags 1 Register I2Cn_INTFL1 0x0010 Bits Name Access Reset Description 31 2 R W Reserved for Future Use Do not modify this field 1 tx...

Page 152: ...s to trigger a RX FIFO threshold event When the number of bytes in the RX FIFO is equal to or greater than this field the hardware sets the I2Cn_INTFL0 rxthi bit indicating an RX FIFO threshold level...

Page 153: ...cription 31 12 R W Reserved for Future Use Do not modify this field 11 8 txth R W 0 TX FIFO Threshold Level Sets the level for a Transmit FIFO threshold event interrupt If the number of bytes remainin...

Page 154: ...disables the TX FIFO Automatic Flush when a NACK is received at the end of a slave transaction 0 The TX FIFO is automatically flushed if a NACK is received at the end of a slave transaction 1 The TX...

Page 155: ...eload Mode is disabled I2Cn_TXCTRL0 txpreld 1 this bit is forced to 1 and the I2C hardware behaves normally Table 12 15 I2 C Data Registers I2C Data Register I2Cn_FIFO 0x002C Bits Name Access Reset De...

Page 156: ...Control I2Cn_CLKLO 0x0034 Bits Name Access Reset Description 31 9 R W 0 Reserved for Future Use Do not modify this field 8 0 scl_lo R W 1 Clock Low Time In Master Mode this configures the SCL low tim...

Page 157: ...t Description 31 16 R W 0 Reserved for Future Use Do not modify this field 15 0 to R W 0 Bus Error SCL Timeout Period Set this value to the number of I2C clock cycles desired to cause a bus timeout er...

Page 158: ...de I2Cn_CTRL0 mst 0 this field must be set as the desired slave address for the peripheral Table 12 22 I2 C DMA Register I2C DMA Register I2Cn_DMA 0x0048 Bits Name Access Reset Description 31 2 R W 0...

Page 159: ...port Wakeup from SLEEP based on configurable Transmit and Receive FIFO Levels Four SPI modes mode 0 1 2 and 3 Programmable Serial Clock SCK frequency and duty cycle Master mode operation up to 60MHz S...

Page 160: ...s an input for receiving data from the Slave In slave mode this signal is an output for transmitting data to the Master SS Slave Select In master mode this signal is an output used to select a slave d...

Page 161: ...etwork SS Slave Select In master mode this signal is an output used to select a slave device prior to communication In slave mode this signal is an input used to indicate an external SPI master is sta...

Page 162: ...the GPIO pin for alternate function operation a SPI0_SCK Set GPIO0_EN 6 to 0 b SPI0_MOSI SISO Set GPIO0_EN 5 to 0 c SPI0_MISO Set GPIO0_EN 4 to 0 i If using three wire SPI this step is not required d...

Page 163: ...n 13 1 Valid settings for SPI0_CLK_CFG scale are 0 to 8 allowing a divisor of 1 to 256 Equation 13 1 SPI Peripheral Clock _ 2 13 3 6 Master Mode Serial Clock Generation In master and multi master mode...

Page 164: ...ck regardless of clock polarity Figure 13 5 SPI Clock Polarity For proper data transmission the clock phase and polarity must be identical for the SPI master and slave The master always places data on...

Page 165: ...3 9 Transfer Format Phase 1 Figure 13 7 is the timing diagram for an SPI transfer in which the clock phase is set SPI0_CTRL2 clk_pha 1 The two SCLK waveforms show active low SPI0_CTRL2 clk_pol 0 and a...

Page 166: ...re SPI read and write transactions are controlled using the SPI FIFO enable bits For a read transaction enable the Receive FIFO and disable the Transmit FIFO 13 3 10 1 Read Transaction Figure 13 8 sho...

Page 167: ...SPI0_DMA rx_fifo_en 0 and enabling the transmit FIFO SPI0_DMA tx_fifo_en 1 The SPI0_MOSI SISO pin is automatically set as to an output by hardware based on the FIFO enable bits Data should be loaded...

Page 168: ...two bytes from the FIFO least significant byte first A 32 bit read from this register dequeues four bytes from the FIFO least significant byte first 13 3 13 SPI Interrupts and Wakeups The SPI support...

Page 169: ...IME R W SPI Slave Select Timing Register 0x0014 SPI0_CLK_CFG R W SPI Master Clock Configuration Register 0x001C SPI0_DMA R W SPI DMA Control Register 0x0020 SPI0_INT_FL R W1O SPI Interrupt Status Flag...

Page 170: ...is ignored 0 Hardware automatically sets this field to 0 when the transaction has been initiated 1 Master initiates a data transmission Ensure that all pending transactions are complete before writin...

Page 171: ...the polarity of the SPI0 SS signal 0 SS is active low 1 SS is active high 15 three_wire R W 0 Three Wire Mode Enable 0 Four wire mode enabled 1 Three wire mode enabled Single IO Mode only 14 R W 0 Res...

Page 172: ...tive to the time SS is active and a new character is transmitted 0 256 1 1 2 2 3 3 254 254 255 255 15 8 ssact2 R W 0 Slave Select Active After Last SCLK Number of system clock cycles that SS is active...

Page 173: ...0 character sizes of 2 and 10 bits are not supported 7 0 lo R W 0x00 SCLK Low Clock Cycles Control 0x0 Low duty cycle control disabled Only valid if SPI0_CLK_CFG scale 0 0x1 0xF Number of internal SPI...

Page 174: ...s currently in the TX FIFO 7 tx_fifo_clear W1O Clear the TX FIFO Set this field to flush the TX FIFO Write 1 only Write 0 is ignored 0 TX FIFO flush not active 1 Clear the TX FIFO and any pending TX F...

Page 175: ...Select Deasserted Flag This flag is set when the slave select pin is deasserted and the SPI is operating in slave mode 4 ssa R W1C 0 Slave Select Asserted Flag This flag is set when the slave select p...

Page 176: ...bled 10 R W 0 Reserved for Future Use Do not modify this field 9 abort R W 0 Slave Mode Abort Detected Interrupt Enable 0 Interrupt is disabled 1 Interrupt is enabled 8 fault R W 0 Multi Master Fault...

Page 177: ...p Enable SPI0_WAKE_EN 0x002C Bits Name Access Reset Description 31 4 R W 0 Reserved for Future Use Do not modify this field 3 rx_full R W 0 Wake on RX FIFO Full Enable 0 Wake event is disabled 1 Wake...

Page 178: ...perations SPI Features Full duplex synchronous communication of 1 to 16 bit characters Four wire interface Data transfers rates up to one fourth the peripheral clock frequency 4 Master and Slave mode...

Page 179: ...ion SCK SPI1_SCK Serial Clock The master generates the Serial Clock signal which is an output from the master and an input to the slave MOSI SPI1_MOSI Master Output Slave Input In master mode this sig...

Page 180: ...cation as shown in Table 14 3 below For a slave I2 S device the SDI signal is used for audio input and the SDO pin is not required For a master I2 S device the SDO pin is used for audio output and the...

Page 181: ...mode Table 14 3 SPIMSS Pins for SPI1 and I2 S SPI Signal I2S Signal Alternate Function Name Alternate Function Number GPIO 16 WLP 20 TQFN SCK WS BCLK SPI1_SCK I2S_BCLK AF2 P0 2 P0 2 MOSI SISO SDO SPI...

Page 182: ...the opposite edge where data is stable Data availability and sampling time is controlled using the SPI phase control field SPIMSS_CTRL phase The SCK clock polarity field SPIMSS_CTRL clkpol controls i...

Page 183: ...e data is shifted into an internal shift register Once a full character is received the character is automatically moved into the receive FIFO Read received data using the SPIMSS_DATA register For out...

Page 184: ...slave select output pin SPI1_SS0 Set SPIMSS_MODE ssv to 1 to set the slave select to active high The typical SPI device uses an active low slave select signal and the SPIMSS_MODE ssv defaults to 0 for...

Page 185: ...nel audio sample after SPIMSS_I2S_CTRL i2s_mute is asserted DMA and FIFO accesses will continue however the data read from the transmit FIFO will be discarded and replaced with zeroes When SPIMSS_I2S_...

Page 186: ...erate a SPIMSS IRQ The SPIMSS Interrupt Flag Register SPIMSS_INT_FL includes the error flags described below 14 5 1 Transmit Overrun A transmit overrun error indicates a write to the transmit FIFO was...

Page 187: ...following interrupt conditions occur 14 6 1 Data Interrupt A data interrupt occurs when a the Transmit FIFO is empty and the transmit shift register shifts out the last bit of the active transmit word...

Page 188: ...equal to 0x02 for SPI and I2 S master operation with a maximum bit rate frequency of 4 Equation 14 1 shows the equation for calculating the SPI master and I2 S master bit rate frequency Equation 14 1...

Page 189: ...ture Use Do not modify this field 7 irqe R W 0 Interrupt Request Enable Set to enable interrupts for the SPIMSS peripheral 0 SPIMSS SPI1 I2S interrupts are disabled 1 SPI MSS SPI1 I2S interrupts are e...

Page 190: ...d valid and is transmitted If data is in the Receive FIFO the data is considered valid and is used as received data 0 Disable SPI1 and I2S 1 Enable SPI1 or I2S if configured Note This bit should be se...

Page 191: ...has occurred Write 1 to clear 0 No FIFO underrun has occurred 1 A FIFO underrun has occurred 1 txst RO 0 Transmit Status This field reads 1 if a SPIMSS data transmission is currently in progress 0 No...

Page 192: ...W 0 Slave Select Value This indicates the value of the SPI1_SSO I2S_LRCLK pin if the SPIMSS slave select pin is configured as an output SPIMSS_MODE ss_io 1 writing this field drives the pin to the val...

Page 193: ...efore activating an RX DMA request 000 Request Receive DMA when RX FIFO contains 1 entry 001 Request Receive DMA when RX FIFO contains 2 entries 010 Request Receive DMA when RX FIFO contains 3 entries...

Page 194: ...5 R W 0 Reserved for Future Use Do not modify this field 4 i2s_lj R W 0 I2S Left Justify 0 Normal I2S audio protocol audio data lags left right channel signal by one SCLK period 1 Audio data is synch...

Page 195: ...AXIM INTEGRATED PRODUCTS INC DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION DEVICES OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT MAXIM ALSO DOES NOT ASSUME LIABIL...

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