MAX32660 User Guide
Maxim Integrated
Page 16 of 195
Figure 3-2: Data Memory Map
3.2
Standard Memory Regions
Many standard memory regions are defined for the Arm Cortex-M4 architecture; the use of many of these is optional for
the system integrator. At a minimum, the MAX32660 must contain code and data memory for application code, stack and
heap usage, as well as certain components which are part of the implemented architecture.
3.2.1
Code Space
The code space area of memory is designed to contain the primary memory used for code execution by the device. This
memory area is defined from byte address range 0x0000 0000 to 0x1FFF FFFF (0.5GB maximum). Two different standard
core bus masters are used by the Arm Cortex-M4 core and the Arm debugger to access this memory area. The I-Code AHB
bus master is used for instruction decode fetching from code memory, while the D-Code AHB bus master is used for data
fetches from code memory. This is arranged so that data fetches avoid interfering with instruction execution.
On the MAX32660, the code space memory area contains the main internal flash memory that typically contains the
instruction code that will be executed on the device. The internal flash memory is mapped into both code and data space
from 0x0000 0000 to 0x0003 FFFF. This program memory area must also contain the default system vector table and the
initial settings for all system exception handlers and interrupt handlers. The reset vector for the device is 0x0000 0000.
