MAX32660 User Guide
Maxim Integrated
Page 194 of 195
SPIMSS DMA Register
SPIMSS_DMA
[0x0018]
Bits
Name
Access
Reset
Description
2:0
tx_fifo_lvl
R/W
0
Transmit FIFO Level
Sets the TX FIFO DMA request threshold. This configures the number of empty TX
FIFO entries before activating a Transmit DMA request.
0b000: Request Transmit DMA when TX FIFO has 1 free entry.
0b001: Request Transmit DMA when TX FIFO has 2 free entries.
0b010: Request Transmit DMA when TX FIFO has 3 free entries.
…
0b111: Request Transmit DMA when TX FIFO has 8 free entries.
Table 14-12: SPIMSS I
2
S Control Register
SPIMSS I2S Control Register
SPIMSS_I2S_CTRL
[0x001C]
Bits
Name
Access
Reset
Description
31:5
-
R/W
0
Reserved for Future Use
Do not modify this field.
4
i2s_lj
R/W
0
I
2
S Left Justify
0: Normal I
2
S audio protocol - audio data lags left/right channel signal by one
SCLK period.
1: Audio data is synchronized with SSEL (left/right channel signal).
3
i2s_mono
R/W
0
I
2
S Monophonic Audio Mode
Set this field to enable monophonic audio mode. In this mode, each transmit data
word is replicated on both left and right channels. Receive data is taken from left
channel, right channel receive data is ignored.
0: Stereophonic audio.
1: Monophonic audio format
2
i2s_pause
R/W
0
I
2
S Pause Transmit/Receive
0: Normal transmission/reception.
1: Halt transmit and receive FIFO and DMA accesses, transmit 0.
1
i2s_mute
R/W
0
I
2
S Mute Transmit
0: Normal transmit.
1: Transmit data is replaced with 0
0
i2s_en
R/W
0
I
2
S Mode Enable
Set to enable I
2
S mode.
0: I
2
S mode is disabled.
1: I
2
S mode enabled.
