MAX32660 User Guide
Maxim Integrated
Page 94 of 195
UART Baud Rate Decimal Register
UARTn_BAUD1
[0x0018]
Bits
Name
Access
Reset
Description
11:0
dbaud
R/W
0
Decimal Portion of Baud Rate Divisor
This field contains the remainder portion of the bit rate divisor. Refer to the
s cti n f r tails f t rmining this fi l ’s valu f r a giv n
bit rate.
Table 8-10: UART FIFO Register
UART FIFO Register
UARTn_FIFO
[0x001C]
Bits
Name
Access
Reset
Description
31:8
-
R/W
0
Reserved for Future Use
Do not modify this field.
7:0
fifo
R/W
N/A
UART FIFO Register
Reading this field reads data from the RX FIFO and writes to this field write to the TX
FIFO.
Table 8-11: UART DMA Configuration Register
UART DMA Configuration Register
UARTn_DMA
[0x0020]
Bits
Name
Access
Reset
Description
31:22
-
R/W
0
Reserved for Future Use
Do not modify this field.
21:16
rxdma_lvl
R/W
0
RX FIFO Level DMA Trigger
If the RX FIFO level is greater than this value, the DMA channel transfers data from the
RX FIFO into memory. DMA transfers continue until the RX FIFO is empty. To avoid an
RX FIFO overrun, do not set this value to 32.
Values above 32 are reserved for future use.
15:14
-
R/W
0
Reserved for Future Use
Do not modify this field.
13:8
txdma_lvl
R/W
0
TX FIFO Level DMA Trigger
If the TX FIFO level is less than this value, the DMA channel transfers data from
memory into the TX FIFO. DMA transfers continue until the TX FIFO is full. To avoid
stalling a UART transmission, do not set this value to 1 or 0.
Values above 32 are reserved for future use.
7:2
-
R/W
0
Reserved for Future Use
Do not modify this field.
1
rxdma_en
R/W
0
RX FIFO DMA Channel Enable
0: RX DMA is disabled
1: RX DMA is enabled
0
txdma_en
R/W
0
TX FIFO DMA Channel Enable
0: TX DMA is disabled
1: TX DMA is enabled
Table 8-12: UART TX FIFO Data Output Register
UART TX FIFO Data Output Register
UARTn_TXFIFO
[0x0024]
Bits
Name
Access
Reset
Description
31:8
-
R/W
0
Reserved for Future Use
Do not modify this field.
