MAX32660 User Guide
Maxim Integrated
Page 18 of 195
On the MAX32660, access to the region that contains most peripheral registers (0x4000 0000 to 0x400F FFFF) goes from the
AHB bus through an AHB-to-APB bridge. This allows the peripheral modules to operate on the slower, easier to handle APB
bus matrix. This also ensures that peripherals with slower response times do not tie up bandwidth on the AHB bus, which
must necessarily have a faster response time since it handles main application instruction and data fetching.
Note: The APB bus supports 32-bit width access only. All access to the APB peripheral register area (0x4000 0000 to
0x400F FFFF) must be 32-bit width only with 32-bit (4 byte) alignment. Access using 8-bit or 16-bit width to this memory
region is not supported and will result in an AHB memory fault exception (returned by the AHB-to-APB bridge interface).
3.2.4
System Area (Private Peripheral Bus)
The system area (private peripheral bus) memory space contains register areas for functions that are only accessible by the
Arm Cortex-M4 core itself (and the Arm debugger, in certain instances). It is defined from byte address range 0xE000 0000
to 0xE00F FFFF. This APB bus is restricted and can only be accessed by the Arm core and core-internal functions. It cannot
be accessed by other modules which implement AHB memory masters, such as the Standard DMA.
In addition to being restricted to the core, application code is only allowed to access this area when running in the
privileged execution mode (as opposed to the standard user thread execution mode). This helps ensure that critical system
settings controlled in this area are not altered inadvertently or by errant code that should not have access to this area.
Core functions controlled by registers mapped to this area include the SysTick timer, debug and tracing functions, the NVIC
(interrupt handler) controller, and the Flash Breakpoint controller.
3.3
Device Memory Instances
This section details physical memory instances on the MAX32660 (including internal flash memory and SRAM instances)
that are accessible as standalone memory regions using either the AHB or APB bus matrix. Memory areas which are only
accessible via FIFO interfaces, or memory areas consisting of only a few registers for a peripheral, are not covered here.
3.3.1
Main Program Flash Memory
The main program flash memory is 256KB in size and consists of 32 logical pages of 8KB each.
3.3.2
Instruction Cache Memory
The internal flash memory instruction cache is 16KB in size and is used to cache instructions fetched using the I-Code bus.
This includes instructions fetched from the internal flash memory. Note that the cache is used for instruction fetches only.
Data fetches (including code literal values) from the internal flash memory do not use the instruction cache.
3.3.3
System SRAM
The system SRAM is 96KB in size and can be used for general purpose data storage, the Arm system stack, USB data
transfers (endpoints), and Standard DMA operations, as well as code execution if desired.
3.3.4
AHB Bus Matrix and AHB Bus Interfaces
This section details memory accessibility on the AHB bus matrix and the organization of AHB master and slave instances.
