MAX32660 User Guide
Maxim Integrated
Page 136 of 195
12.3.10
SCL Clock Configurations
The SCL frequency is dependent upon the values of I
2
C peripheral clock and the values of the external resistor and capacitor
on the SCL clock line.
Note: An external RC load on the SCL line will affect the target SCL frequency calculation.
Figure 12-3: I
2
C Specification Minimum and Maximum Clock Parameters for Standard and Fast Mode
Parameter
Standard Mode
Fast Mode
Min
Max
Min
Max
SCL Clock Freq.
0
100 kHz
0
400 kHz
I
2
C Hold Time
4.0 µs
-
0.6 µs
-
SCL High
4.0 µs
-
0.6 µs
-
SCL Low
4.7 µs
-
1.3 µs
-
t
RC
Rise Time
-
1000 ns
20 ns
300 ns
12.3.11
Clock Synchronization
The I
2
C specification allows for more than one bus master. When more than one master is on the same bus, clock
synchr nizati n b tw n iff r nt mast r’s cl cks is n c ssary.
The I
2
C Master mode supports automatic clock
synchronization and is compliant with the clock synchronization requirements of the I
2
C Specification. Clock synchronization
is automatically handled in the I
2
C controller.
12.3.12
Transmit and Receive FIFOs
Each I
2
C master/slave has one 8-byte deep transmit FIFO (TX FIFO) and one 8-byte deep receive FIFO (RX FIFO) that reduces
processor overhead. To further speed transfers, the DMA can read and write to each FIFO. When the DMA is used to read
and write to the FIFOs, no additional I
2
C configuration is required and interrupts are still sent to the core. See the DMA
section for more details.
When the receive FIFO is enabled, received bytes are automatically written to it. If the receive FIFO is full, no more data is
written and any newly received bytes are lost.
When the transmit FIFO is enabled, either user firmware or the DMA can provide data to be transmitted. The oldest byte in
the FIFO is sent out over SDA only when an ACK signal is received from an addressed slave.
Interrupts can be generated for the following FIFO status:
•
TX FIFO level less than or equal to threshold
•
RX FIFO level greater than or equal to threshold
•
TX FIFO underflow
•
RX FIFO overflow
•
TX FIFO locked for writing
12.4
Clock Stretching
If a slave cannot receive or transmit a complete byte of data, it can force the master into a wait state by clock stretching.
Clock stretching is when a slave holds SCL low after an ACK is on the bus. When the slave is ready, it releases the SCL line
from low and then resumes the data transfer.
