MAX32660 User Guide
Maxim Integrated
Page 171 of 195
Table 13-8: SPI Transmit Packet Size Register
SPI Transmit Packet Size Register
SPI0_CTRL1
[0x0008]
Bits
Name
Access
Reset
Description
31:16
rx_num_char
R/W
0
Number of Receive Characters
Number of characters to receive in RX FIFO.
Note: If the SPI port is set to operate in 4-wire mode, this field is ignored and the
tx_num_chars field is used for both the number of characters to receive or
transmit.
15:0
tx_num_char
R/W
0
Number of Transmit Characters
Number of characters to transmit from TX FIFO.
Note: In 4-wire mode, this also applies to the RX FIFO.
Table 13-9: SPI Static Configuration Registers
SPI Static Configuration Register
SPI0_CTRL2
[0x000C]
Bits
Name
Access
Reset
Description
31:17
-
R/W
0
Reserved for Future Use
Do not modify this field.
16
ss_pol
R/W
0
Slave Select Polarity
Controls the polarity of the SPI0 SS signal
0: SS is active low
1: SS is active high
15
three_wire
R/W
0
Three-Wire Mode Enable
0: Four-wire mode enabled.
1: Three-wire mode enabled (Single IO Mode only).
14
-
R/W
0
Reserved for Future Use
Do not modify this field.
13:12
data_width
R/W
0
SPI Data Width
Set this field to the required number of SDIO pins required. For Three-wire mode
this field must be set to 0. Four-wire SPI mode supports Single or Dual IO Mode.
0: 1-data pin (Single IO Mode - MOSI)
1: 2-data pins (Dual IO Mode - MOSI/MISO)
2: Reserved
3: Reserved
11:8
num_bits
R/W
0x0
Number of Bits per Character
1-bit and 9-bit character lengths are not supported in Slave Mode
7:2
-
R/W
0
Reserved for Future Use
Do not modify this field.
1
clk_pol
R/W
0
Clock Polarity
Selects the SPI clock polarity.
0: Normal clock. Use when in SPI Mode 0 and Mode 1
1: Inverted clock. Use when in SPI Mode 2 and Mode 3
0
clk_pha
R/W
0
Clock Phase
0: Data sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2
1: Data sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3
