MAX32660 User Guide
Maxim Integrated
Page 181 of 195
14.2
SPIMSS Configuration
Before configuring the SPIMSS peripheral, first disable any SPIMSS activity by setting the
.enable
field to 0.
14.2.1
SPIMSS Pin Configuration for SPI and I
2
S Operation
Pin selection and configuration is required to use the SPIMSS for either SPI or I
2
S operation. The following information
applies to both I
2
S or SPI operation.
shows the pin selection options for the SPIMSS (SPI1/I
2
S) for each package
available. The Alternate Function Name column maps the typical SPI signal name to the Alternate Function name on the
MAX32660 family of parts. The required pins for SPIMSS are all mapped to Alternate Function 2 on GPIO Port 0 and are
available on the same pins in both the 16-WLP and the 20-TQFN as shown in
For SPI operation, an external pull-up resistor should be used to prevent floating input signals when operating the SPI
signals in open drain mode (refer to the
wor
bit) or high impedance mode.
When the SPI or I
2
enable
= 0, all the SPI1 pins are put into high-impedance mode.
Table 14-3: SPIMSS Pins for SPI1 and I
2
S
SPI Signal
I
2
S Signal
Alternate
Function
Name
Alternate
Function
Number
GPIO
16-WLP
20-TQFN
SCK
WS
(BCLK)
SPI1_SCK (I2S_BCLK)
AF2
P0.2
P0.2
MOSI (SISO)
SDO
SPI1_MOSI (I2S_SDO)
AF2
P0.1
P0.1
MISO
SDI
SPI1_MISO (I2S_SDI)
AF2
P0.0
P0.0
SS
BCLK
(LRCLK)
SPI1_SS0 (I2S_LRCLK)
AF2
P0.3
P0.3
Four-wire SPI uses SCK, MISO, MOSI, and the SS pin. I
2
S requires BCLK, LRCLK and either SDO or SDI. The following steps
outline setting up the GPIO pins for the SPI1/I
2
S alternate function usage.
1.
Set the GPIO pin for alternate function operation.
a.
SPI1_SCK (I2S_BCLK): Set GPIO0_EN[2] to 0.
b.
SPI1_MOSI (I2S_SDO): Set GPIO0_EN[1] to 0.
c.
SPI1_MISO (I2S_SDI): Set GPIO0_EN[0] to 0.
d.
SPI1_SS0 (I2S_LRCLK): Set GPIO0_EN[3] to 0.
2.
Select AF2 using the GPIO0_AF_SEL register.
a.
SPI1_SCK (I2S_BCLK):: Set GPIO0_AF_SEL[2] to 1
b.
SPI1_MOSI (I2S_SDO): Set GPIO0_AF_SEL[1] to 1.
c.
SPI1_MISO (I2S_SDI):: Set GPIO0_AF_SEL[0] to 1.
d.
SPI1_SS0 (I2S_LRCLK): Set GPIO0_AF_SEL[3] to 1.
14.3
SPI Operation
SPI is a full-duplex, synchronous, character-oriented serial communication channel that supports a four-wire interface
consisting of a serial clock, SCK, a slave select line, SS, and two data lines, MOSI and MISO. The SPIMSS consists of a transmit
and receive shift register, a transmit FIFO, a receive FIFO, a bit rate generator and a control unit as shown in
