Maxim Integrated MAX32660, User Manual

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MAX32660 User Guide
Maxim Integrated Page 145 of 195
Offset Register Name Access Description
[0x0034] I2Cn_CLKLO R/W I 2 C Clock Low Time Register
[0x0038] I2Cn_CLKHI R/W I 2 C Clock High Time Register
[0x003C] I2Cn_HS_CLK R/W I 2 C Hs-Mode Clock Control Register
[0x0040] I2Cn_TIMEOUT R/W I 2 C Timeout Register
[0x0044] I2Cn_SLADDR R/W I
2
C Slave Address Register
[0x0048] I2Cn_DMA R/W I 2 C DMA Enable Register
1.1.2 I
2
C Register Details
Table 12-4: I
2
C Control Registers 0
I
2
C Control 0 Register I2Cn_CTRL0 [0x0000]
Bits Name Access Reset Description
31:16 - R/W 0
Reserved for Future Use
Do not modify this field.
15 hsmode R/W 0
High Speed Mode
Set this field to 1 to enable High-speed mode (Hs-mode) operation. This field must be
set to 0 for Standard, Fast or Fast-Plus operation.
0: Hs-mode not enabled.
1: Hs-mode enabled.
14 - R/W 0
Reserved for Future Use
Do not modify this field.
13 scl_ppm R/W 0
SCL Push-Pull Mode Enable
Setting this field enables push-pull mode for the SCL hardware pin. This field should
not be set unless any external slave device will never actively drive SCL low.
0: SCL operates in standard I 2 C open-drain mode
1: SCL operates in push-pull mode without the need for a pull-up resistor. Only
recommended when in Master mode and external slaves will not drive SCL low.
12 scl_strd R/W 0
SCL Clock Stretch Control
0: Enable Slave clock stretching
1: Disable Slave clock stretching
11 read R 0
Read/Write Bit Status
Returns the logic level of the R/W bit on a received address match
(
I2Cn_INTFL0 . ami = 1) or general call match ( I2Cn_INTFL0 . gci = 1). This bit is valid for
three SCL clock cycles after the address match status flag is set.
10 swoe R/W 0
Software output Enabled
When set, pins SDA and SCL are directly controlled by the fields I2Cn_CTRL0 .sdao and
I2Cn_CTRL0 .sclo , rather than the I
2
C controller. Setting this field to 1 enables software
bit bang control of I 2 C.
0: The I 2 C controller manages the SDA and SCL pins in hardware.
1: SDA and SCL are controller by firmware using the I2Cn_CTRL0 .sdao and
I2Cn_CTRL0 .sclo fields.
9 sda RO -
SDA Status
Returns the current logic level of the SDA pin.
0: SDA pin is logic low.
1: SDA pin is logic high.