Maxim Integrated MAX32660, User Manual

Page: 175 / 195

MAX32660 User Guide
Maxim Integrated Page 175 of 195
SPI Interrupt Flag Register SPI0_INT_FL [0x0020]
Bits Name Access Reset Description
13 tx_und R/W1C 0
TX FIFO Underrun Flag
Set if SPI is in Slave Mode, and a read from empty TX FIFO is attempted. If SPI0 is in
Master Mode, this bit is not set as the SPI stalls the clock until data is written to the
empty TX FIFO.
Note: This condition should be avoided by using the SPI0_INT_FL .tx_level interrupt flag
to ensure that the underrun condition does not occur.
12 tx_ovr R/W1C 0
TX FIFO Overrun Flag
Set when a write is attempted to a full TX FIFO.
0: Condition has not occurred.
1: Condition occurred. Write 1 to clear.
11 m_done R/W1C 0
Master Data Transmission Complete Flag
Set if SPI is in Master Mode and all data transmission is complete.
10 - R/W 0
Reserved for Future Use
Do not modify this field.
9 abort R/W1C 0
Slave Mode Transaction Abort Detected Flag
Set if the SPI is in Slave Mode, and SS is deasserted before a complete character is
received.
8 - R/W1C 0
Reserved for Future Use
Do not modify this field.
7:6 - R/W 0
Reserved for Future Use
Do not modify this field.
5 ssd R/W1C 0
Slave Select Deasserted Flag
This flag is set when the slave select pin is deasserted and the SPI is operating in slave
mode.
4 ssa R/W1C 0
Slave Select Asserted Flag
This flag is set when the slave select pin is asserted and the SPI is operating in slave
mode.
1: Slave Select pin is asserted from a deasserted state.
3 rx_full R/W1C 0
RX FIFO Full Flag
This flag is set when the RX FIFO is full. Write 1 to clear. Clearing this flag and not
reading data from the RX FIFO will result in this flag being set by hardware
automatically when another byte is received on the SPI port.
1: RX FIFO is full.
2 rx_level R/W1C 0
RX FIFO Threshold Level Crossed Flag
Set when the RX FIFO exceeds the level set in the SPI0_DMA .rx_fifo_level .
1 tx_empty R/W1C 1
TX FIFO Empty Flag
This field is set when the Transmit FIFO is empty. Write 1 to clear. This flag must be
cleared by the application directly. Writing data to the TX FIFO does not clear this flag
automatically.
Note: On the MAX32660 SPI0 port, the SPI0_DMA .tx_fifo_level should be used to avoid
an empty TX FIFO condition.
0 tx_level R/W1C 0
TX FIFO Threshold Level Crossed Flag
Set when the TX FIFO is less than the value in SPI0_DMA .tx_fifo_level. Write 1 to clear.
This flag must be cleared by the application explicitly. Correcting the condition by
writing data to the TX FIFO does not clear this flag.