MAX32660 User Guide
Maxim Integrated
Page 90 of 195
Table 8-5: UART Status Register
UART Status Register
UARTn_STAT
[0x0008]
Bits
Name
Access
Reset Description
31:25
-
RO
0
Reserved for Future Use
Do not modify this field.
24
rx_to
RO
0
RX Timeout
This field is set to 1 when a receive timeout occurs. This field is set by hardware when
the condition occurs and is automatically cleared when the condition is no longer
valid.
23:22
-
RO
0
Reserved for Future Use
Do not modify this field.
21:16
tx_num
RO
0
Number of Bytes in the TX FIFO
Read this field to determine the number of bytes in the transmit FIFO.
15:14
-
RO
0
Reserved for Future Use
Do not modify this field.
13:8
rx_num
RO
0
Number of Byes in RX FIFO
Read this field to determine the number of bytes in the receive FIFO.
7
tx_full
RO
0
TX FIFO Full Status Flag
This field reads 1 when the TX FIFO is full. This field is set by hardware when the
condition occurs and is automatically cleared when the condition is no longer valid.
0: TX FIFO is not full.
1: TX FIFO is full.
6
tx_empty
RO
1
TX FIFO Empty Flag
This field reads 1 when the TX FIFO is empty. This field is set by hardware when the
condition occurs and is automatically cleared when the condition is no longer valid.
0: TX FIFO is not empty,
tx_num
> 0.
1: TX FIFO is empty.
5
rx_full
RO
0
RX FIFO Full Flag
This field reads 1 when then RX FIFO is full. This field is set by hardware when the
condition occurs and is automatically cleared when the condition is no longer valid.
0: RX FIFO is not full.
1: RX FIFO is full.
4
rx_empty
RO
1
RX FIFO Empty Flag
This flag reads 1 when the RX FIFO is empty.
3
break
RO
0
Break Flag
This field is set when a break condition occurs.
0: BREAK not received.
1: BREAK condition received.
2
parity
RO
0
Parity Bit State
This field returns the state of the parity bit.
0: Parity bit is 0.
1: Parity bit is 1.
1
rx_busy
RO
0
RX Busy
This field reads 1 when the UART is receiving data.
0: UART is not actively receiving data.
1: UART is actively receiving data.
