MAX32660 User Guide
Maxim Integrated
Page 29 of 195
wakeup logic, and interrupts are disabled. The Always-on Domain (AoD) is disabled as well. The device only recovers
through a Power-On Reset (POR) which re-initializes the device.
.mode
= 6 results in the part immediately entering Shutdown State.
4.7
Device Resets
Four device resets are available:
•
Peripheral Reset
•
Soft Reset
•
System Reset
•
Power-On Reset
On completion of any of the four reset cycles, all peripherals are reset, HCLK and PCLK are operational, the CPU core
receives clocks and power, and the device enters
ACTIVE
mode. Program execution begins at the reset vector address.
Each peripheral in the MAX32660 can be reset individually by firmware using the
and
registers.
4.7.1
Peripheral Reset
This resets all peripherals. The CPU retains its state. The GPIO, Watchdog Timers, RAM Retention, and Global Control
Registers (GCR), including the clock configuration, are unaffected.
Initiate a Peripheral Reset by setting
.periph_rst
to 1.
4.7.2
Soft Reset
This is the same as a Peripheral Reset except that it also resets the GPIO to its Power-On Reset state. All alternate functions
are tri-stated.
Initiate a Soft Reset by setting
.soft
to 1.
4.7.3
System Reset
This is the same as Soft Reset and additionally resets all GCR registers, resetting the clocks to their default state. The CPU
state is reset as well as the watchdog timers. The AoD and RAM Retention are unaffected.
A watchdog timer reset event initiates a System Reset. To start a System Reset from the application, set
system
= 1.
4.7.4
Power-On Reset
A POR resets everything in the device to its power-on reset default state.
shows the effects of the four reset types
and the four power modes supported by the MAX32660.
Table 4-6: Reset and Low Power Mode Effects
Peripheral
Reset
Soft
Reset
System
Reset
POR
ACTIVE
Mode
SLEEP
Mode
DEEPSLEEP
Mode
BACKUP
Mode
GCR Registers
No
No
Reset
Reset
N/A
N/A
N/A
N/A
