MAX32660 User Guide
Maxim Integrated
Page 85 of 195
8.3
UART Interrupts
Interrupts can be generated for the following conditions:
•
The Transmit FIFO level is equal or less than the set transmit threshold.
•
The Receive FIFO level is equal or greater than the set receieve threshold.
•
The Receive FIFO is overrun, which means the Receive FIFO is full but is still receiving data
•
Any CTS state change. During Hardware Flow Control, this interrupt is generated either because:
−
CTS is deasserted, which tells the UART to pause transmitting data
−
CTS is asserted, which tells the UART to resume transmitting data
•
A Receive Parity Error occurred
•
A Receive Frame Error occurred, which means START or STOP bits were not detected
•
A Receive Timeout condition occurred, which means the RX FIFO has not received a character for a set time
•
First and Last BREAK characters
8.4
UART Bit Rate Calculation
The UART peripheral clock,
𝑓
𝑃𝐶𝐿𝐾
, is used as the input clock to the UART bit rate generator. The following fields are used to
set the target bit rate for the UART.
•
.clk_div
selects the bit rate clock divisor.
•
.ibaud
sets the integer portion of the bit rate divisor.
•
.dbaud
sets the decimal portion of the bit rate divisor.
are used to determine the values for each of the bit rate fields required to
achieve a target bit rate for the UART.
Equation 8-1: UART Bit Rate Divisor Equation
𝐷𝐼𝑉 =
𝑓
𝑈𝐴𝑅𝑇_𝐵𝐼𝑇_𝑅𝐴𝑇𝐸_𝐶𝐿𝐾
(𝐶𝑙𝑜𝑐𝑘 𝐷𝑖𝑣𝑖𝑑𝑒𝑟 × 𝑇𝑎𝑟𝑔𝑒𝑡 𝐵𝑖𝑡 𝑅𝑎𝑡𝑒)
Note:
.clkdiv should be set to the highest value that results in
⌊𝐷𝐼𝑉⌋ ≥ 1
to achieve the highest accuracy for
the target bit rate.
Equation 8-2: Bit Rate Integer Calculation
𝑈𝐴𝑅𝑇𝑛_𝐵𝐴𝑈𝐷0. 𝑖𝑏𝑎𝑢𝑑 = ⌊𝐷𝐼𝑉⌋
Equation 8-3: Bit Rate Remainder Calculation
𝑈𝐴𝑅𝑇𝑛_𝐵𝐴𝑈𝐷1. 𝑑𝑏𝑎𝑢𝑑 = (𝐷𝐼𝑉 − 𝑈𝐴𝑅𝑇𝑛_𝐵𝐴𝑈𝐷0. 𝑖𝑏𝑎𝑢𝑑) × 128
8.4.1
Example Baud Rate Calculation:
𝑇𝑎𝑟𝑔𝑒𝑡 𝐵𝑖𝑡 𝑅𝑎𝑡𝑒 = 1,843,200 𝑏𝑖𝑡𝑠 𝑝𝑒𝑟 𝑠𝑒𝑐𝑜𝑛𝑑 (1.8 𝑀𝑏𝑝𝑠)
𝑓
𝐵𝐼𝑇_𝑅𝐴𝑇𝐸_𝐶𝐿𝐾
= 𝑓
𝑃𝐶𝐿𝐾
= 48 𝑀𝐻𝑧
𝐷𝐼𝑉 =
48,000,000
(𝐶𝑙𝑜𝑐𝑘 𝐷𝑖𝑣𝑖𝑑𝑒𝑟 × 1,843,200)
, 𝑤ℎ𝑒𝑟𝑒 𝐶𝑙𝑜𝑐𝑘 𝐷𝑖𝑣𝑖𝑑𝑒𝑟 = 2
(7−𝑐𝑙𝑘𝑑𝑖𝑣)
