Maxim Integrated MAX32660, User Manual

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MAX32660 User Guide
Maxim Integrated Page 77 of 195
7.11 Channel and Register Access Restrictions
Writing to any register while a channel is disabled is supported, but there are certain restrictions when a channel is enabled.
The
DMAn_STAT .ch_st bit indicates whether the channel is enabled or not.
Because an active channel might be in the middle of an AHB read/write burst, do not write to the DMAn_SRC , DMAn_DST ,
or DMAn_CNT registers while a channel is active ( DMAn_STAT .ch_st = 1).
To disable any DMA channel, clear the DMAn_CFG .chen bit. Then, poll the DMAn_STAT .ch_st bit to verify that the channel is
disabled.
7.12 Memory-to-Memory DMA
Memory-to-memory transfers are completed as if the request is always active. This means that the DMA channel generates
an almost constant request for the bus until its transfer is complete. For this reason, assign a lower priority to channels
executing memory-to-memory transfers to prevent starvation of other DMA channels.
7.13 Standard DMA Control Registers
The DMA base peripheral address is 0x4002 8000. Refer to Table 3-1: APB Peripheral Base Address Map for the addresses of
all APB mapped peripherals.
Table 7-6: Standard DMA Control Registers, Offsets, Access and Descriptions
Offset Register Access Description
[0x0000] DMA_INT_EN R/W DMA Control register
[0x0004] DMA_INT_FL RO DMA Interrupt Status register
7.13.1 Standard DMA Control Register Details
Table 7-7: DMA Interrupt Enable Register
DMA Interrupt Enable Register DMA_INT_EN [0x0000]
Bits Name Access Reset Description
31:4 - RO 0 Reserved for Future Use
Do not modify this field.
3:0 chien R/W 0 Channel Interrupt Enable
Each bit in this field enables the corresponding channel interrupt.
0: Channel interrupt disabled
1: Channel interrupt enabled
Table 7-8: DMA Interrupt Flag Register
DMA Interrupt Flag Register DMA_INT_FL [0x0004]
Bits Name Access Reset Description
31:4 - RO 0 Reserved for Future Use
Do not modify this field.