Maxim Integrated MAX32660, User Manual

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MAX32660 User Guide
Maxim Integrated Page 81 of 195
Table 7-12: DMA Status Register
DMA Status Register DMAn_STAT [0x0104]
Bits Name Access Reset Description
31:7 - RO 0 Reserved for Future Use
Do not modify this field.
6 to_st R/W1C 0 Time-Out Status
A time-out occurred if this field reads 1. Write 1 to clear.
0: No time out
1: A time out has occurred
5 - RO 0 Reserved for Future Use
Do not modify this field.
4 bus_err R/W1C 0 Bus Error
If this bit reads 1, an AHB abort occurred and the channel was disabled by hardware.
Reading this bit indicates the following:
0: No error found
1: An AHB bus error occurred
3 rld_st R/W1C 0 Reload Status
This bit is set by hardware when reload is enabled and a reload occurred. Write 1 to
clear.
0: Reload event has not occurred.
1: Reload event occurred.
2 ctz_st R/W1C 0 CTZ Status
This bit is set by hardware when a Count-to-zero (CTZ) has occurred, if enabled. Write
1 to clear.
0: CTZ has not occurred
1: CTZ has occurred
1 ipend RO 0 Channel Interrupt
This field is set when any enabled channel interrupt occurs. When this field is set,
examine the other fields in this register,
DMAn_STAT , to determine the cause of the
Channel Interrupt. Clearing the status bits in this register clears this field. This field is
read-only.
0: No channel interrupt pending.
1: Channel Interrupt pending.
0 ch_st RO 0 Channel Status
This bit is used to indicate when it is safe to change the configuration, address, and
count registers for the channel. This field is read-only.
Hardware clears this bit automatically when the channel is not active. When hardware
clears this bit, hardware also clears the
DMAn_CFG .chen bit.
0: Channel configuration can be changed.
1: Channel not safe to change configuration.