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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
ECLKSYNCB Usage in VHDL
Component Instantiation
Library lattice;
use lattice.components.all;
Component and Attribute Declaration
COMPONENT ECLKSYNCB
PORT (ECLKI :IN STD_LOGIC;
STOP :IN STD_LOGIC;
ECLKO :OUT STD_LOGIC);
END COMPONENT;
ECLKSYNCB Instantiation
I1: ECLKSYNCB
port map (
ECLKI => ECLKI
,STOP => STOP
,ECLKO => ECLKO);
ECLKSYNCB Usage in Verilog
Component and Attribute Declaration
module ECLKSYNCB (ECLKI,STOP,ECLKO);
input ECLKI;
input STOP;
output ECLKO;
endmodule
ECLKSYNCB Instantiation
ECLKSYNCB ECLKSYNCInst0 (
.ECLKI (ECLKI)
,.STOP (STOP)
,.ECLKO (ECLKO));
General Routing for Clocks
The ECP5 and ECP5-5G device architecture supports the ability to use data routing, or general routing, for a clock.
This capability is intended to be used for small areas of the design to allow additional flexibility in linking dedicated
clocking resources and building very small clock trees. General routing cannot be used for edge clocks for applica-
tions that use the DDR registers in the I/O components of the FPGA.
Software will limit the distance of a general routing based (gated) clock to one PLC in distance to a primary clock
entry point. If the software cannot place the clock gating logic close enough to a primary clock entry point then an
error will occur:
ERROR – par: Unable to reach a primary clock entry point for general route clock <net> in the minimum required
distance of one PLC.
There are multiple entry points to the Primary clock routing throughout the ECP5 and ECP5-5G device fabric. In
this case it is recommended to add a preference for this gated clock to use primary routing.
Figure 21. Gated Clock to the Primary Clock Routing
Clock
So
u
rce
Primary
Clock Tree
CIB
Entry
General
Ro
u
ting
Logic
Logic
Logic
Logic
Clock
Ro
u
ting
