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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
CLKDIVF Instantiation
attribute DIV : string;
attribute DIV of I1 : label is “2.0”;
attribute GSR : string;
attribute GSR of I1 : label is “DISABLED”;
I1: CLKDIVF
generic map (DIV => “2.0”
,GSR => “DISABLED”)
port map (RST => RST
,CLKI => CLKI
,ALIGNWD => ALIGNWD
,CDIVX => CDIVX);
CLKDIVF Usage in Verilog
Component and Attribute Declaration
module CLKDIVF (RST, CLKI, ALIGNWD, CDIVX);
parameter DIV = “2.0”; // “2.0”, “3.5”
parameter GSR = “DISABLED”; // “ENABLED”, “DISABLED
input RST, CLKI, ALIGNWD;
output CDIVX;
endmodule
CLKDIVF Instantiation
defparam I1.DIV = “2.0”;
defparam I1.GSR = “DISABLED”;
CLKDIVF I1 (
.RST (RST)
,.CLKI (CLKI)
,.ALIGNWD (ALIGNWD)
,.CDIVX (CDIVX));
Edge Clock Bridge (ECLKBRIDGECS)
ECLK Clock Bridge provides to bridge the ECLK for banks on the same side or the ECLK of the left side and the
right side. The ECLK Bridge enhances the communication of high speed clocks of the two edges with minimum
skew to ECLK tree.
There are two ECLK bridge components in the ECP5 and ECP5-5G device. There are two ECLK muxes on the left
and two ECLK muxes on the right and they allow a user to bridge edge clocks to the left and right sides of the chip
with minimal skew.
In the edge clock bridge there is a non-glitchless clock select mux that allows a design to switch between two differ-
ent clock sources for each edge clock. This clock select mux is instantiated using the ECLKBRIDGECS primitive.
Not all edge clocks can drive the ECLKBRIDGECS, one of the two ECLKs on the left and right side can be bridged.
When connected to the ECLKBRIDGECS it would use up the ECLK1 of both banks on the left side and ECLK0 of
both banks on the right side of the device.
