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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
OSCG Usage in Verilog
Component and Attribute Declaration
module OSCG (OSC);
output OSC;
endmodule
OSCG Instantiation
OSCG I1 (.OSC(OSC))
Edge Clocks
Each ECP5 and ECP5-5G device I/O bank has four ECLK resources. These clocks, which have low injection time
and skew, are used to clock I/O registers. Edge clock resources are designed for high speed I/O interfaces with
high fan-out capability. Refer to Appendix B. EDGE CLOCK Sources and Connectivity for detailed information on
the ECLK locations and connectivity.
The sources of edge clocks are:
• Dedicated Clock (PCLK) pins
• DLLDEL output
• PLL outputs (CLKOP & CLKOS)
• ECLK Bridge
• Internal nodes
The ECP5 and ECP5-5G device has Edge Clock (ECLK) at the Left side and right side of the device. There are two
ECLK network per bank IO. ECLK Input MUX collects all clock sources available shown in figure below. There are
two ECLK Input MUXs, one on the left side and one on the right side. Each of these MUX will generate total of four
ECLK Clock sources. Two of them drive the upper IO bank and two of them drive the lower IO bank. Two out of four
also drive the ECLK Bridge Switch Block to form an ECLK Bridge high speed clock before drive the ECLK Tree Net-
work.
Figure 16. Edge Clock Sources Per Bank
Top Left/ Right PCLK Pin
Top Right/Left PLL CLKOP
Top Left/ Right DLLDEL O
u
tp
u
t
Top Right/Left PLL CLKOS
Bottom Right/Left PLL CLKOP
Bottom Right/Left PLL CLKOS
Bottom Left/ Right PCLK Pin
Bottom Left/ Right DLLDEL O
u
tp
u
t
From Ro
u
ting
ECLKSY
N
C
To ECLK of other
b
ank on same side
To ECLKBRIDGE to go
to other side
From
ECLKBRIDGE
From ECLK of
other
b
ank on
same side
ECLK Tree
