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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
Overview of Other Clocking Elements
Edge Clock Dividers (CLKDIVF)
Clock dividers are provided to create the divided down clocks used with the I/O Mux/DeMux gearing logic (SCLK
inputs to the DDR) and drives to the Primary Clock routing to the fabric. There are four clock dividers on the ECP5
and ECP5-5G device.
PCS Clock Dividers (PCSCLKDIV)
A new clock divider is provided to create phase-matched divided-down clocks for bus-widening/narrowing circuits.
A port is provided to dynamically change the divide value of the input clock. The PCSCLKDI
V
will mainly be used to
slow the clock rate from high speed SERDES applications by providing the clocks for domain crossing circuits.
There is one PCSCLKDI
V
per SERDES on an LFE5UM device.
Dynamic Clock Select (DCSC)
The ECP5 and ECP5-5G dynamic clock select provides run-time selectable glitchless or non-glitchless operation
between two independent clock sources to the primary clock network. This clock select allows the selection of clock
sources without leaving the dedicated clock resources in the device. There are two dynamic clock select blocks on
the ECP5 and ECP5-5G device.
Edge Clock Bridge with Clock Select (ECLKBRIDGECS)
The ECLKBRIDGECS allows non-glitchless ECLK selection between two ECLKs. The ECLKBRIDGECS will allow
user bridge ECLK from one side to the other. There are two of these elements and they are used for ECLK clock
bridging and ECLK selection.
Edge Clock Stop (ECLKSYNCB)
Each ECLK has a block to allow dynamic stopping of the edge clock. This allows the user to start and stop the
clock synchronous to an event or external signal. These are important for applications requiring exact clock timing
relationships on the inputs, such as DDR memories and video applications.
Oscillator (OSCG)
An internal programmable rate oscillator is provided. The oscillator can be used for master configuration modes
when the FPGA sources the configuration clock, Soft Error Detect (SED), and as a user logic clock source that is
available after FPGA configuration. There is one OSCG on the ECP5 and ECP5-5G device. The oscillator clock
output is routed directly to primary clocking.
The oscillator output is not a high-accuracy clock, having a +/- 15% variation in its output frequency. It is mainly
used for circuits that do not require a high degree of clock accuracy. Examples of usage would be asynchronous
logic blocks such as a timer or reset generator, or other logic that require a constantly running clock.
