7
ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
Figure 5. Primary Clock Routing Architecture
The centermux can source up to 16 independent primary clocks per quadrant which can clock the logic located in
that quadrant. The centermux can also route each clock source to all quadrants. The Diamond software will auto-
matically route a primary clock to all four quadrants in the FPGA.
Dedicated Clock Inputs
The ECP5 and ECP5-5G device has dedicated pins, called PCLK pins, to bring an external clock source into the
FPGA and allow them to be used as FPGA primary clocks. These inputs route directly to the Primary clock net-
work, or to Edge clock routing resources. A dedicated PCLK clock pin must always be used to route an external
clock source to FPGA logic and I/O.
If an external input clock is being sourced to a PLL, then in most cases the input clock should use a dedicated PLL
input pin. SERDES reference clocks also have dedicated SERDES reference clock pins. The ECP5 and ECP5-5G
device allows a PLL reference clock or a SERDES reference clock to come from an external Primary Clock (PCLK)
pin and route through the Primary clock network to drive the reference clock to the SERDES or the input of a PLL.
PCS Clock Dividers (PCSCLKDIV)
The ECP5 and ECP5-5G device has a new clock divider called the PCSCLKDI
V
. The PCSCLKDI
V
is built with our
PCS / IP Core interaction in mind. Its main purpose is to allow our IP cores to do multi-rate clocking for cores that
can change data rates. The specific features are:
• Capability to generate different divider clocks
• Input mux to change the divider value on-the-fly.
• Non-glitchless when the divider’s select mux input is changed.
• Data width changes in the fabric for widening / narrowing circuits. This element must allow clock domain crossing
in the fabric registers.
Center MUX
Quadrant TL
Quadrant BL
Quadrant TR
Quadrant BR
Mid
MUX
Fa
b
ric
Entry
Fa
b
ric
Entry
Fa
b
ric
Entry
Fa
b
ric
Entry
14
12
16
16
16
16
14
Primary Clock Ro
u
ting to Fa
b
ric Reso
u
rces in
TR Q
u
adrant of the FPGA
Primary Clock Ro
u
ting to Fa
b
ric Reso
u
rces in
TL Q
u
adrant of the FPGA
Primary Clock Ro
u
ting to Fa
b
ric Reso
u
rces in
TL Q
u
adrant of the FPGA
Primary Clock Ro
u
ting to Fa
b
ric Reso
u
rces in
TL Q
u
adrant of the FPGA
Mid
MUX
Mid
MUX
Mid
MUX
Primary Clock So
u
rces Into the Mid-M
u
x
Primary Clock So
u
rces Into the Mid-M
u
x
Primary Clock
So
u
rces
Into the Mid-M
u
x
Primary Clock
So
u
rces
Into the Mid-M
u
x
