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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
Figure 33. ECP5 and ECP5-5G PLL Optional Ports Configuration Tab
Table 20. Tab 3, PLL Optional Ports, Clarity Designer GUI
User Parameters
Description
Range
Default
Corresponding
HDL Attribute
Enable Clock Select
Enables the input clock mux (PLLREFCS
component).
ON / OFF
OFF
Dynamic Phase ports
Provides Dynamic Phase Shift ports.
ON / OFF
OFF
DPHASE_SOURC
E
Clock Enable OP
Provides ENCLKOP; clock enable port
for dynamic clock output shutoff.
ON / OFF
OFF
Clock Enable OS
Provides ENCLKOS; clock enable port
for dynamic clock output shutoff.
ON / OFF
OFF
Clock Enable OS2
Provides ENCLKOS2; clock enable port
for dynamic clock output shutoff.
ON / OFF
OFF
Clock Enable OS3
Provides ENCLKOS3; clock enable port
for dynamic clock output shutoff.
ON / OFF
OFF
Provide Standby Port
Provides STDBY port to put the PLL into
standby mode.
ON / OFF
OFF
STDBY_ENABLE
Provide PLL Reset
Provides RST signal.
ON / OFF
OFF
PLLRST_ENA
Provide PLL Lock Signal Provides the LOCK signal.
ON / OFF
OFF
PLL Lock is Sticky
Once LOCK goes high it won’t de-assert
unless the PLL is reset.
ON / OFF
OFF
PLL_LOCK_MODE
