4
ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
sysCLOCK PLL Overview
The sysCLOCK PLLs can be used in a variety of clock management applications such as clock injection removal,
clock phase adjustment, clock timing adjustment, and frequency synthesis (multiplication and division of a clock).
The ECP5 and ECP5-5G Clarity Designer PLL GUI shows important timing parameters such as the
V
CO rate and
the PLL loop bandwidth.
PLL Input sources are:
• Dedicated PLL Input Pins
• Primary Clock Routing
• Edge Clock Routing
• FPGA Fabric
Figure 2. ECP5 and ECP5-5G PLL Block Diagram
There are four PLLs on the bigger density devices LFE5-85 and LFE5-45 and two PLLs on the smaller density
LFE5-25 device. There is one PLL on each corner of the device on the bigger density devices and the smaller den-
sity devices have one PLL only on the Lower Left and Lower Right corner. Each PLL has four outputs. All four PLL
outputs can go to the Primary Clock network. Only the CLKOP and CLKOS outputs can go to the ECLK network.
Refclk Di
v
ider M
Phase
Detector,
VCO, and
Loop Filter
CLKOP
Di
v
ider
(1-12
8
)
Lock
Detect
Feed
b
ack
Clock Di
v
ider
CLK0
CLK1
SEL
Refclk
E
N
CLKOP
CLKOP
CLKOS
CLKOS2
CLKOS3
CLKI
PLLCSOUT
PLLREFCS
VCO
CLKFB
FBKSEL
CLKOS
Di
v
ider
(1-12
8
)
CLKOS2
Di
v
ider
(1-12
8
)
CLKOS3
Di
v
ider
(1-12
8
)
VCO
VCO
VCO
Internal Feed
b
ack
CLKOP, CLKOS, CLKOS2, CLKOS3
RST
STDBY
PHASESTEP
PHASEDIR
PHASESEL[1: 0]
Dynamic
Phase
Adj
u
st
PHASELOADREG
LOCK
E
N
CLKOS
E
N
CLKOS2
E
N
CLKOS3
CLKI
CLKI2
