28
ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
Figure 26. RST Input Timing Diagram
Dynamic Clock Enables
Each PLL output has a user input signal to dynamically enable / disable its output clock glitchlessly. When the clock
enable signal is set to logic ‘0’, the corresponding output clock is held to logic ‘0’.
Table 14. PLL Clock Output Enable Signal List
This allows the user to save power by stopping the corresponding output clock when not in use. The clock enable
signals are optional and will only be available if the user has selected the corresponding option in Clarity Designer.
If a clock enable signal is not requested, its corresponding output will be active at all times when the PLL is instan-
tiated unless the PLL is placed into standby mode. The user cannot access a clock enable signal in Clarity
Designer when using it for external feedback in order to avoid shutting off the feedback clock input.
STDBY Input
The STDBY signal is used to put the PLL into a low power standby mode when it is not required. The STDBY signal
is optional and will only be available if the user has selected the Standby port option in Clarity Designer. The
STDBY signal is active high. When asserted the PLL outputs are pulled to “0” and the PLL will be reset. Users
need to stay in the STDBY mode for at least 1 ms to make sure the PLL analog circuits are fully reset and to have
a stable analog startup.
Dynamic Phase Shift Inputs
The ECP5 and ECP5-5G PLL has five ports to allow for dynamic phase adjustment from FPGA logic. The Dynamic
Phase Adjustment section will elaborate on how the user should drive these ports.
PHASESEL Input
The PHASESEL[1:0] inputs are used to specify which PLL output port will be affected by the dynamic phase
adjustment ports. The settings available are shown in the Dynamic Phase Adjustment section. The PHASESEL
signal must be stable for 5 ns before the PHASESTEP or PHASELOADREG signals are pulsed. The PHASESEL
signal is optional and will be available if the user has selected the “Dynamic Phase Ports” option in Clarity
Designer.
Table 15. PHASESEL signal settings definition
Clock Enable Signal Name
Corresponding PLL Output
Clarity Designer Option Name
ENCLKOP
CLKOP
“Clock Enable OP”
ENCLKOS
CLKOS
“Clock Enable OS”
ENCLKOS2
CLKOS2
“Clock Enable OS2”
ENCLKOS3
CLKOS3
“Clock Enable OS3”
PHASESEL[1:0]
PLL Output Shifted
00
CLKOS
01
CLKOS2
10
CLKOS3
11
CLKOP
Trst
Trstrec
CLKI
CLKOP/OS/
OS2/OS3
RST
