10
ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
PCSCLKDIV Usage in VHDL
Component Instantiation
Library lattice;
use lattice.components.all;
Component and Attribute Declaration
component PCSCLKDIV
Generic (GSR : string);
Port (RST : in STD_LOGIC;
CLKI : in STD_LOGIC;
SEL : in STD_LOGIC_VECTOR(2 downto 0);
CDIV1 : in STD_LOGIC;
CDIVX : out STD_LOGIC);
end component;
PCSCLKDIV Instantiation
attribute GSR : string;
attribute GSR of I1 : label is “DISABLED”;
I1: PCSCLKDIV
generic map (
GSR => “DISABLED”)
port map (
RST => RST
,CLKI => CLKI
,SEL => SEL
,CDIV1 => CDIV1
,CDIVX => CDIVX);
PCSCLKDIV Usage in Verilog
Component and Attribute Declaration
module PCSCLKDIV (RST, CLKI, SEL, CDIV1, CDIVX);
parameter GSR = “DISABLED”;// “ENABLED”, “DISABLED”
input RST, CLKI;
input [2:0] SEL;
output CDIVX;
endmodule
PCSCLKDIV Instantiation
defparam I1.GSR = “DISABLED”;
PCSCLKDIV I1 (
.RST (RST)
,.CLKI (CLKI)
,.SEL (SEL)
,.CDIV1 (CDIV1)
,.CDIVX (CDIVX));
