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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
LOCK Output
The LOCK output provides information about the status of the PLL. After the device is powered up and the input
clock is valid, the PLL will achieve lock within 16 ms. Once lock is achieved, the PLL LOCK signal will be asserted.
The LOCK signal can be set in Clarity Designer in either the default “unsticky” frequency lock mode by checking the
“Provide PLL Lock Signal” or sticky lock mode by selecting “PLL Lock is Sticky”. In sticky lock mode, once the
LOCK signal is asserted (logic ‘1’) it will stay asserted until a PLL reset is asserted. In the default lock mode of
“unsticky” frequency lock, if during operation the input clock or feedback signals to the PLL become invalid the PLL
will lose lock and the LOCK output will de-assert (logic ‘0’). It is recommended to assert PLL RST to re-synchronize
the PLL to the reference clock when the PLL loses lock. The LOCK signal is available to the FPGA routing to imple-
ment the generation of the RST signal if requested by the designer. The LOCK signal is optional and will be avail-
able if the user has selected the Provide PLL Lock signal option in Clarity Designer.
Dynamic Phase Adjustment
Dynamic phase adjustment of the PLL output clocks can be affected without reconfiguring the FPGA by using the
dedicated dynamic phase-shift ports of the PLL.
All four output clocks, CLKOP, CLKOS, CLKOS2 & CLKOS3 have the dynamic phase adjustment feature but only
one output clock can be adjusted at a time. Table above shows the output clock selection settings available for the
PHASESEL[1:0] signal. The PHASESEL signal must be stable for 5 ns before the PHASESTEP or PHASELOAD-
REG signals are pulsed.
The selected output clock phase will either be advanced or delayed depending upon the value of the PHASEDIR
port or signal. Table 16 shows the PHASEDIR settings available. The PHASEDIR signal must be stable for 5 ns
before the PHASESTEP or PHASELOADREG signals are pulsed.
VCO Phase Shift
Once the PHASESEL and PHASEDIR have been set, a
V
CO phase adjustment is made by toggling the PHAS-
ESTEP signal from the current setting. Each pulse of the PHASESTEP signal will generate a phase step based on
this equation:
(CLKO<n>_FPHASE/(8*CLKO<n>_DIV)]*360
Where <n> is the clock output specified by PHASESEL (CLKOP/OS/OS2/OS3).
V
alues for CLKO<n>_FPHASE
and CLKO<n>_DI
V
are located in the HDL source file.
The PHASESTEP signal is latched in on the falling edge and is subject to a minimum wait of four
V
CO cycles prior
to pulsing the signal again. One step size is the smallest phase shift that can be generated by the PLL in one pulse.
The dynamic phase adjustment results in a glitch free adjustment when delaying the output clock, but glitches may
result when advancing the output clock.
Figure 27. PLL Phase Shifting Using the PHASESTEP Signal
CLKOP
PHASESTEP
CLKOS
Shifted Phase
Minim
u
m 5ns Set
u
p Time
Hold Minim
u
m 4 VCO
Cycles
PHASESEL
[1:0]
PHASEDIR
“01”
Hold Minim
u
m 4 VCO
Cycles
