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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
ECLKBRIDGECS Component Definition
The ECLKBRIDGECS component must be instantiated in the source code of a design in order to bridge Edge
clocks. Figure 18 and Table 11 define the ECLKBRIDGECS.
Note that an ECLKSYNCB module has to be always used after the ECLKBRIDGECS instance to be able to con-
nect to the ECLK tree.
Figure 18. ECLKBRIDGECS Component Symbol
Table 11. ECLKBRIDGECS Component Port Definition
ECLKBRIDGECS Usage in VHDL
Component Instantiation
Library lattice;
use lattice.components.all;
Component and Attribute Declaration
COMPONENT ECLKBRIDGECS
PORT (CLK0 :IN STD_LOGIC;
CLK1 :IN STD_LOGIC;
SEL :IN STD_LOGIC;
ECSOUT :OUT STD_LOGIC);
END COMPONENT;
ECLKBRIDGECS Instantiation
I1: ECLKBRIDGECS
port map (
CLK0 => CLK0
,CLK1 => CLK1
,SEL => SEL
,ECSOUT => ECSOUT);
ECLKBRIDGECS Usage in Verilog
Component and Attribute Declaration
module ECLKBRIDGECS (CLK0,CLK1,SEL,ECSOUT);
input CLK0;
input CLK1;
input SEL;
output ECSOUT;
endmodule
Port Name
I/O
Description
CLK0
I
Clock Input Port 0 – Default
CLK1
I
Clock Input Port 1
SEL
I
Select Port
—
SEL = 0 for CLK0
—
SEL = 1 for CLK1
ECSOUT
O
Clock Output Port
ECLKBRIDGECS
CLK 0
CLK 1
SEL
ECSOUT
