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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
Figure 25. PLL Dedicated Inputs to the PLLREFCS Component for Top Left and Right PLL
This adds a lot of flexibility for designs that need to switch between two external clocks.
Standby Mode
The ECP5 and ECP5-5G device PLL contains a Standby Mode that allows the PLL to be placed into a standby
state to save power when not needed in the design. Standby mode is very similar to holding the PLL in reset since
the
V
CO will be turned off and will need to regain lock when exiting standby. In both cases, reset and standby
mode, the PLL will retain its programming.
Users MUST hold the PLL in standby for a minimum of 1 ms in order to be sure the PLL analog circuits are fully
reset and to have a stable analog startup.
PLL Inputs and Outputs
CLKI Input
The CLKI signal is the reference clock for the PLL. It must conform to the specifications in the data sheet in order
for the PLL to operate correctly. The CLKI signal can come from a dedicated PLL input pin or from internal routing.
The dedicated dual-purpose I/O pin provides a low skew input path and is the recommended source for the PLL.
The reference clock can be divided by the input (M) divider to create one input to the phase detector of the PLL.
CLKFB Input
The CLKFB signal is the feedback signal to the PLL. The feedback signal is used by the Phase Frequency Detector
inside the PLL to determine if the output clock needs adjustment to maintain the correct frequency and phase. The
CLKFB signal can come from a primary clock net (feedback mode = CLKO[P/S/S2/S3]) to remove the primary
clock routing injection delay, from a dedicated external dual-purpose I/O pin (feedback mode = UserClock) to
account for board level clock alignment, or an internal PLL connection (feedback mode = INT_O[P/S/S2/S3]) for
simple feedback. The feedback clock signal will be divided by the feedback (N) divider to create an input to the
V
CO of the PLL. A bypassed PLL output cannot be used as the feedback signal.
RST Input
At power-up an internal power-up reset signal from the configuration block resets the PLL. At runtime an active
high, asynchronous, user-controlled PLL reset signal can be provided as a part of the PLL module. The RST signal
can be driven by an internally generated reset function or by an I/O pin. This RST signal resets the PLL core (
V
CO,
phase detector, and charge pump) and the output dividers which will cause the outputs to be logic ‘0’. In bypass
mode the output will not be reset.
After the RST signal is de-asserted the PLL will start the lock-in process and will take tLOCK time, about 16 ms, to
complete PLL lock. Figure below shows the timing diagram of the RST input. The RST signal is active high. The
RST signal is optional. Trst = 1 ms reset pulse width, Trstrec = 1 ns time after a reset before the divider output
starts counting again.
CLK 0
CLK 1
SEL
PLLREFCS
PLL 0
CLKI
Primary Clock Inp
u
ts
Edge Clock Inp
u
ts
Fa
b
ric Inp
u
ts
Dedicated
External
PLL Inp
u
t 0
Dedicated
External
PLL Inp
u
t 1
PLLCSOUT
