5
ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
PLL Features
Dedicated PLL Inputs
The PLLs have dedicated PLL input pins that are not Primary Clock input pins. Each of the Top Left and Right cor-
ner PLLs have two pairs of dedicated PLL input pins, one from the Left/Right side bank and the other from the Top
bank. Either one of these can be used as input to the PLL.
The bottom two PLLs have one pair of dedicated input pin on the Left/Right side banks.
Figure 3. PLL Input Pins for LFE5UM/LFE5UM5G-85 and LFE5UM/LFE5UM5G-45
Figure 4. PLL Input Structure for LFE5-25
Input PLL Clock Selection (PLLREFCS)
The PLLREFCS component is a non-glitchless multiplexor that allows the user to dynamically select between two
PLL input reference clocks. The PLLREFCS has the same input clock sources as the PLL. Since the dedicated
PLL inputs are routed to the input of the PLLREFCS components a user can dynamically select between two exter-
nal reference clock inputs for the top corners of the FPGA. This mux can also be used stand-alone with the PLL in
bypass mode for more clock muxing capabilities.
Clock Injection Delay Removal
The clock injection delay removal feature of the PLL removes the delay associated with the PLL and clock tree.
This feature is typically used to reduce clock to out timing and remove the delay differences between the PLL out-
put clock and the data input. This feature is performed by aligning the input clock with a feedback clock from the
clock tree. Optional delay may also be added to the feedback path to further reduce the clock injection time.
Clock Phase Adjustment
The clock phase adjustment feature of the PLL provides the ability to set a specific phase offset between the out-
puts of the PLL. New to the ECP5 and ECP5-5G device, phase adjustments can be calculated in much finer incre-
ments since the frequency is used to calculate the available phase increments. This feature is detailed further in
the Dynamic Phase Adjustment section.
Q
u
adrant TL
Q
u
adrant BL
Q
u
adrant TR
Q
u
adrant BR
CLKI
PLL0
0
CLKI
Dedicated External PLL Inp
u
t 0
PLL
0
CLKI
PLL
0
CLKI
P
0P
P
C
LK
I
Dedicated External PLL Inp
u
t 1
Primary Clock/Edge Clock/Fa
b
ric Inp
u
ts
Dedicated External PLL Inp
u
t 0
Primary Clock/Edge Clock/Fa
b
ric Inp
u
ts
Dedicated External PLL Inp
u
t 0
Dedicated External PLL Inp
u
t 1
Primary Clock/Edge Clock/Fa
b
ric Inp
u
ts
Dedicated External PLL Inp
u
t 0
Primary Clock/Edge Clock/Fa
b
ric Inp
u
ts
PLL_BR
PLL_BL
PLL_TL
PLL_TR
PLL0
Q
u
adrant TL
Q
u
adrant BL
Q
u
adrant TR
Q
u
adrant BR
PLL0
0
CLKI
PLL
0
CLKI
Dedicated External PLL Inp
u
t 0
Primary Clock/Edge Clock/Fa
b
ric Inp
u
ts
Dedicated External PLL Inp
u
t 0
Primary Clock/Edge Clock/Fa
b
ric Inp
u
ts
PLL_BR
PLL_BL
