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Lattice Semiconductor sysCLOCK ECP5, Usage Manual

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ECP5 and ECP5-5G sysCLOCK 

PLL/DLL Design and Usage Guide

PHASEDIR Input

The PHASEDIR input is used to specify which direction the dynamic phase shift will occur, advanced (leading) or 
delayed (lagging). When PHASEDIR = 0 then the phase shift will be delayed. When PHASEDIR = 1 then the phase 
shift will be advanced. The PHASEDIR signal must be stable for 5 ns before the PHASESTEP or PHASELOAD-
REG signals are pulsed. The PHASEDIR signal is optional and will be available if the user has selected the 
Dynamic Phase ports option in Clarity Designer.

Table 16. PHASEDIR signal settings definition

PHASESTEP Input

The PHASESTEP signal is used to initiate a 

V

CO dynamic phase shift for the clock output port and in the direction 

specified by the PHASESEL and PHASEDIR inputs. This phase adjustment is done by changing the phase of the 

V

CO in 45

o

 increments. The 

V

CO phase changes on the negative edge of the PHASESTEP input after four 

V

CO 

cycles. This is an active low signal and the minimum pulse width (both high and low) of PHASESTEP pulse is four 
cycles of 

V

CO running period. The PHASESTEP signal is optional and will be available if the user has selected the 

Dynamic Phase ports option in Clarity Designer. The PHASESEL and PHASEDIR are required to have a setup 
time of 5 ns prior to PHASESTEP falling edge.

PHASELOADREG Input

The PHASELOADREG signal is used to initiate a post-divider dynamic phase shift, relative to the unshifted output, 
for the clock output port and in the direction specified by the PHASESEL and PHASEDIR inputs. A phase shift is 
started on the falling edge of the PHASELOADREG signal and there is a minimum pulse width of 10 ns from asser-
tion to deassertion. The PHASESEL and PHASEDIR are required to have a setup time of 5 ns prior to PHASEL-
OADREG falling edge.The PHASELOADREG signal is optional and will be available if the user has selected the 
Dynamic Phase ports option in Clarity Designer.

PLL Clock Outputs

The PLL has four outputs, listed in Table 17. All four outputs can be routed to the Primary clock routing of the 
FPGA. All four outputs can be phase shifted statically or dynamically if external feedback on the clock is not used. 
They can also statically or dynamically adjust their output duty cycle. The outputs can come from their output 
divider or the reference clock input (PLL bypass). In bypass mode the output divider can be bypassed or used to 
divide the reference clock.

Table 17. PLL Clock Outputs and ECLK Connectivity

PHASEDIR

Direction

0

Delayed (lagging)

1

Advanced (leading)

Clock Output Name

Edge Clock Connectivity

Selectable Output

CLKOP

Right, Left ECLKs

Always Enabled

CLKOS

Right, Left ECLKs

Selectable via Clarity Designer

CLKOS2

No ECLK Connection

Selectable via Clarity Designer

CLKOS3

No ECLK Connection

Selectable via Clarity Designer

Summary of Contents for sysCLOCK ECP5

Page 1: ...date their pinout so that correct pin placement is used The Lattice Diamond tools should be used to validate the pinout while designing the printed circuit board Clock Control Distribution Network ECP...

Page 2: ...d to the fabric in the quadrant Initially the Lattice Diamond software automatically routes each clock to all four quadrants up to a maximum of 16 clocks since each clock is routed to all four quadran...

Page 3: ...the ECP5 and ECP5 5G device Edge Clock Bridge with Clock Select ECLKBRIDGECS The ECLKBRIDGECS allows non glitchless ECLK selection between two ECLKs The ECLKBRIDGECS will allow user bridge ECLK from...

Page 4: ...LFE5 85 and LFE5 45 and two PLLs on the smaller density LFE5 25 device There is one PLL on each corner of the device on the bigger density devices and the smaller den sity devices have one PLL only o...

Page 5: ...This feature is typically used to reduce clock to out timing and remove the delay differences between the PLL out put clock and the data input This feature is performed by aligning the input clock wit...

Page 6: ...ng to the primary clock routing by a mid mux There are 56 mid mux connections and four FPGA fabric connections 60 total routed to a multiplexor in the center of the chip called the centermux From the...

Page 7: ...n and route through the Primary clock network to drive the reference clock to the SERDES or the input of a PLL PCS Clock Dividers PCSCLKDIV The ECP5 and ECP5 5G device has a new clock divider called t...

Page 8: ...cks route directly to the input of the PCSCLKDIV without requiring the use of a primary clock The CDIV1 and CDIVX outputs route directly to the primary clock routing Its function is to do bus widening...

Page 9: ...Component Port Definition Table 3 PCSCLKDIV Component Attribute Definition Port Name I O Description CLKI I Clock Input RST I Reset input Active High Asynchronously forces all outputs low RST 0 Clock...

Page 10: ...DIVX out STD_LOGIC end component PCSCLKDIV Instantiation attribute GSR string attribute GSR of I1 label is DISABLED I1 PCSCLKDIV generic map GSR DISABLED port map RST RST CLKI CLKI SEL SEL CDIV1 CDIV1...

Page 11: ...at the clock source used as feedback into the GPLL should not be switched when using the DCS as it will lead to loss of lock for the GPLL As indicated there are two modes of clock switching In non gli...

Page 12: ...CLK0 CLK1 SEL 3 0 0001 0010 DCSOUT 0001 SEL 3 0 Changes to 0010 Wait for CLK0 falling edge Switch output at CLK1 falling edge SEL 3 0 Changes to 0001 Wait for CLK1 falling edge Switch output at CLK0 f...

Page 13: ...design as defined in this section Figure 12 DCSC Component Symbol Table 4 DCSC Component Port Definition Port Name I O Description CLK0 I Clock Input port 0 Default CLK1 I Clock Input port 1 SEL 1 0 I...

Page 14: ...C_VECTOR 1 downto 0 MODESEL IN STD_LOGIC DCSOUT OUT STD_LOGIC END COMPONENT DCSC Instantiation attribute DCSMODE string attribute DCSMODE of DCSinst0 label is POS I1 DCSC generic map DCSMODE POS port...

Page 15: ...the primary clock network Also this dynamic clock control function can be disabled by a configuration memory fuse to always enable the primary clock network This DCC controls the clock sources from th...

Page 16: ...attice components all Component and Attribute Declaration COMPONENT DCCA PORT CLKI IN STD_LOGIC CE IN STD_LOGIC CLKO OUT STD_LOGIC END COMPONENT DCCA Instantiation I1 DCCA port map CLKI CLKI CE CE CLK...

Page 17: ...uting through the left mid mux It can be configured for operation at a wide range of frequencies via configuration bits OSCG Component Definition The OSCG component can be instantiated in the source c...

Page 18: ...ECLK at the Left side and right side of the device There are two ECLK network per bank IO ECLK Input MUX collects all clock sources available shown in figure below There are two ECLK Input MUXs one o...

Page 19: ...able 9 CLKDIVF Component Port Definition Table 10 CLKDIVF Component Attribute Definition The ALIGNWD input is intended for use with high speed data interfaces such as DDR or 7 1 LVDS Video CLKDIVF Usa...

Page 20: ...r banks on the same side or the ECLK of the left side and the right side The ECLK Bridge enhances the communication of high speed clocks of the two edges with minimum skew to ECLK tree There are two E...

Page 21: ...in VHDL Component Instantiation Library lattice use lattice components all Component and Attribute Declaration COMPONENT ECLKBRIDGECS PORT CLK0 IN STD_LOGIC CLK1 IN STD_LOGIC SEL IN STD_LOGIC ECSOUT...

Page 22: ...ted in the source code of a design as defined in this section Assert ing the STOP control signal has the ability to stop the edge clock in order to synchronize the signals derived from ECLK and used i...

Page 23: ...areas of the design to allow additional flexibility in linking dedicated clocking resources and building very small clock trees General routing cannot be used for edge clocks for applica tions that u...

Page 24: ...are four at the left side and right side four at the top side of the device These pins can be used when user runs out of PCLK pins Note that for any DDR interface it is still required to use dedicate...

Page 25: ...PLL RST I Resets the whole PLL ENCLKOP I Enable PLL output CLKOP ENCLKOS I Enable PLL output CLKOS ENCLKOS2 I Enable PLL output CLKOS2 ENCLKOS3 I Enable PLL output CLKOS3 PLLWAKESYNC I Enable PLL swit...

Page 26: ...Similar restriction would apply on other clocks Phase Adjustment Dynamic Mode The phase adjustments can also be controlled in a dynamic mode using the PHASESEL PHASEDIR PHAS ESTEP and PHASELOADREG po...

Page 27: ...L to determine if the output clock needs adjustment to maintain the correct frequency and phase The CLKFB signal can come from a primary clock net feedback mode CLKO P S S2 S3 to remove the primary cl...

Page 28: ...e Standby port option in Clarity Designer The STDBY signal is active high When asserted the PLL outputs are pulled to 0 and the PLL will be reset Users need to stay in the STDBY mode for at least 1 ms...

Page 29: ...ing edge PHASELOADREG Input The PHASELOADREG signal is used to initiate a post divider dynamic phase shift relative to the unshifted output for the clock output port and in the direction specified by...

Page 30: ...CLKOP CLKOS CLKOS2 CLKOS3 have the dynamic phase adjustment feature but only one output clock can be adjusted at a time Table above shows the output clock selection settings available for the PHASESEL...

Page 31: ...ve been set a post divider phase adjustment is made by toggling the PHASELOADREG signal Each pulse of the PHASELOADREG signal will generate a phase shift The step size relative to the unshifted output...

Page 32: ...l is driven high and the outputs will be driven low Users need to stay in the STDBY mode for at least 1 ms to make sure the PLL analog circuits are fully reset and to have a stable analog startup The...

Page 33: ...y will be displayed in the Actual Frequency text box If an entered value is out of range it will be dis played in red and an error message will be displayed The user can also select a tolerance value...

Page 34: ...ption Range Default Corresponding HDL Attribute CLKI Frequency Input 10 400 MHz 100 MHz FREQUENCY_PIN _CLKI Refclk Divider Read Only Shows the reference clock divider value CLKI_DIV Enable High Band w...

Page 35: ...0 5 0 10 0 0 0 Actual Frequency read only CLKOS2 Enable ON OFF OFF CLKOS2_Enable Bypass ON OFF OFF OUTDIVIDER_MU XC Clock Divider read only CLKOS2_DIV Desired Frequency 1 3 125 400 MHz 100 MHz FREQUE...

Page 36: ...Fre quency 100 MHz CLKOP_CPHASE CLKOP_FPHASE Actual Phase read only CLKOS Desired Phase 1 Based on Fre quency 100 MHz CLKOS_CPHASE CLKOS_FPHASE Actual Phase read only CLKOS2 Desired Phase 1 Based on...

Page 37: ...for dynamic clock output shutoff ON OFF OFF Clock Enable OS Provides ENCLKOS clock enable port for dynamic clock output shutoff ON OFF OFF Clock Enable OS2 Provides ENCLKOS2 clock enable port for dyn...

Page 38: ...unt pulses through depend ing on when the clock is switched It is expected that the input clocks have the same frequency Table 22 defines the I O ports of the PLLREFCS block This component is instanti...

Page 39: ...hnical support case through www latticesemi com techsupport Revision History Date Version Change Summary November 2015 1 1 Added support for ECP5 5G Changed document title to ECP5 and ECP5 5G sysCLOCK...

Page 40: ..._0 PCLK0_1 D C S D C S Centermux 16 16 PLL_TL OS2 PLL_TL OS3 PLL_TL OP PLL_TL OS ulq_pclkcib0 ulq_pclkcib1 lrq_pclkcib0 lrq_pclkcib1 urq_pclkcib0 urq_pclkcib1 tlq_pclkcib0 tlq_pclkcib1 trq_pclkcib0 tr...

Page 41: ...q_pclkcib0 trq_pclkcib1 Mid Mux DCU1 rx_clk0 DCU1 rx_clk1 DCU1 tx_clk0 DCU0 tx_clk1 DCU0 rx_clk0 DCU0 rx_clk1 DCU0 tx_clk0 DCUCLKDIV0 C1 brq_pclkcib0 brq_pclkcib1 Mid Mux llc_pclkcib0 DCC DCC DCC DCC...

Page 42: ...lkcib1 tlq_pclkcib0 tlq_pclkcib1 trq_pclkcib0 trq_pclkcib1 Mid Mux DCU0 tx_clk1 DCU0 rx_clk0 DCU0 rx_clk1 DCU0 tx_clk0 DCUCLKDIV0 C1 brq_pclkcib0 brq_pclkcib1 Mid Mux llc_pclkcib0 DCC DCC DCC DCC 16 1...

Page 43: ...r the Dual Function section you will see the PCLK and PLL input pins listed as below Primary Clock Input Pin PCLKT Bank _ 0 1 Dedicated PLL Input Pin LOC _GPLL0T_IN Table 22 Clock Input Selection Tabl...

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