KUNBUS-COM EtherCAT
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parameters CPOL (Clock polarity) and CPHA (Clock Phase) in
COMS-Modul and define these permanently via the CDI Menu
[
}
102] or memory register [
}
60]. The bit sequence (MSB first or
MSB last) is fixed for COMS modules, the module always starts the
transmission with the MSB (bit of highest value) of a byte. All bytes
belonging to a block are transmitted in a continuous sequence. The
clock signal required is input to PIN a4 externally from the Master.
The COMS-Modul can process maximum clock frequencies of
20 MHz.
Handshaking
The handshaking lines ensure that a Master first sends the
subsequent transmission block after the module has processed the
block that was received previously.
The module indicates by the "low" level on the SPI ready line that a
transmission cycle has been completed, the status of the last
transmission is waiting to be retrieved and the Master can trigger the
next cycle. The Master starts this cycle by setting the SSC Chip
Select line to "high" to indicate to the module that data is ready for
transmission and the following data block is meant for the module
(theoretically, a master can address several modules). Once the
module is now ready for this data transmission, it sets the SPI ready
line to "high" and the Master can start transmission of the block
immediately. A maximum delay between setting the CS signal and
releasing by the ready signal of the module is 10 ms. All bytes of a
data block are now transmitted directly in succession at the rate
preset by the Master. After the last bit of the data block has been
transmitted, the Master indicates the end of the transmission by
resetting the SPI Chip Select line to "low". The module responds to
this by resetting the SPI Ready line to "low". This happens at the
earliest, however (maximum 10 ms after resetting CS), when the
data has been processed insofar as the status was determined and
is ready in the SPI output buffer so that the next transmission can
start. This must first be requested, however, by the Master (as
described above) by setting the SPI Chip Select line to "high".
Chip Select
(Master)
Ready
(Slave)
Data
(Master & Slave)
Components
