Keysight U2741A, Programmer'S Reference Manual

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SCPI Status Registers 2
Keysight U2741A Programmer’s Reference Guide 21
Status Byte Register
The Status Byte summary register reports conditions from the other status
registers. Query data that is waiting in the U2741A output buffer is immediately
reported through message available bit (bit 4). Bits in the summary register are
not latched. Clearing an event register will clear the corresponding bits in the
Status Byte summary register. Reading all messages in the output buffer,
including any pending queries, will clear the message available bit.
Bit Definitions: Status Byte Register
The Status Byte summary register will be cleared when:
– You execute the clear status (
*CLS
) command.
– Querying the Standard Event register (
*ESR?
command will clear only bit 4 in
the Summary Register)
The Status Byte Enable register is cleared when you execute the
*SRE 0
command.
Bit number Decimal value Definition
0 Not Used 1 Always zero
1 Not Used 2 Always zero
2 Error Queue 4 There is at least one error code in the error queue
3 Not Used 8 Always zero
4 Message Available 16 Data is available in the U2741A output buffer
5 Standard Event 32 One or more bits are set in the Standard Event register (bits must
be enabled in Standard Event enable register)
6 Master Summary 64 One or more bits are set in Status Byte Register and may generate
a Request for Service (RQS)
7 Standard Operation Summary 128 One or more bits are set in the Standard Operation Register (bits
must be enabled in Standard Operation enable register)