8XC196L
X SUPPLEMENT
8-10
(J_CFG.7) and considers whether the IFR message response has a CRC byte appended. Figure
8-7 depicts the SAE preferred, active-level state bit format timing for the NB.
Figure 8-7. Huntzicker Symbol Definition for the Normalization Bit
8.4.1.4
Start and End Message Frame Symbols
Five symbols are used to mark the start and end of a message frame and to allow the J1850 bus
to properly recognize the interruption of a message transmission or reception. Figure 8-8 illus-
trates the formats and their respective timing.
The following is a description of each symbol:
•
start of frame (SOF) — this symbol signals the start of a message frame. This is an active-
level state symbol only and appears once per frame.
•
end of data (EOD) — this symbol signals the end of the data transmission. This is a passive-
level state symbol only. It appears twice in IFR messaging: at the end of the initial request
data field and at the end of the IFR data field.
•
end of frame (EOF) — this symbol signals the end of a message frame and returns the bus
to an idle state. This is a passive-level state symbol only. It appears once per frame.
•
in-frame separation (IFS) — the timing of this symbol allows for proper synchronization of
multiple nodes during back-to-back transmissions. Nodes contending for the bus must
comply with one of two conditions before transmitting:
— wait for the IFS minimum timing to expire
— wait for a rising edge on the bus after the EOF minimum timing has expired
•
break (BRK) — this symbol signals an interruption during a bus transmission. At the point
of termination, all nodes are reset. This is an active-level state symbol.
A5220-01
0
1
NB for IFR with CRC
128µS
0
1
or
NB for IFR without CRC
64µS
Summary of Contents for 87C196CA
Page 9: ...1 Guide to This Manual...
Page 10: ......
Page 13: ...2 Architectural Overview...
Page 14: ......
Page 22: ......
Page 23: ...3 Address Space...
Page 24: ......
Page 33: ...4 Standard and PTS Interrupts...
Page 34: ......
Page 43: ...5 I O Ports...
Page 44: ......
Page 51: ...6 Synchronous Serial I O Port...
Page 52: ......
Page 56: ......
Page 57: ...7 Event Processor Array...
Page 58: ......
Page 65: ...8 J1850 Communications Controller...
Page 66: ......
Page 89: ...9 Minimum Hardware Considerations...
Page 90: ......
Page 93: ...10 Special Operating Modes...
Page 94: ......
Page 98: ......
Page 99: ...11 Programming the Nonvolatile Memory...
Page 100: ......
Page 106: ......
Page 107: ...A Signal Descriptions...
Page 108: ......
Page 118: ......
Page 119: ...Glossary...
Page 120: ......
Page 133: ...Index...
Page 134: ......