manualshive.com logo in svg

Intel 87C196CA, Supplement To User’S Manual

Share
Download
Intel 87C196CA Supplement To User’S Manual Download Page 68

8XC196L

X SUPPLEMENT

8-2

The J1850 controller can handle network protocol functions including message frame sequenc-
ing, bit arbitration, in-frame response (IFR) messaging, error detection, and delay compensation.

The J1850 communications controller (Figure 8-2) consists of a control state machine (CSM),
symbol synchronization and timing (SST) circuitry, six control and status registers, transmit and
receive buffers, and an interrupt handler.

Figure 8-2. J1850 Communications Controller Block Diagram

A5169-01

Peripheral Data Bus

J_CFG

J_CMD

J_RX

JRX_BUF

JTX_BUF

J_TX

J_STAT

J_DLY

Interrupt

Handler

J1850ST

J1850RX

J1850TX

OVR

UNDR

TX

RX

Bus Error

Error

Detection

Circuitry

Bit

Arbitration

Circuitry

Cyclic

Redundancy

Check Circuitry

CSM

Symbol

Encoder

Symbol

Decoder

Prescaler

Delay

Compensator

SST

Digital

Filter

Internal Clocking

TXJ1850

RXJ1850

J1850 Communications Controller

Summary of Contents for 87C196CA

Page 1: ...8XC196Lx Supplement to 8XC196Kx 8XC196Jx 87C196CA User s Manual August 2004 Order Number 272973 003...

Page 2: ...ice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility w...

Page 3: ...E 3 1 ADDRESS PARTITIONS 3 1 3 2 REGISTER FILE 3 2 3 3 PERIPHERAL SPECIAL FUNCTION REGISTERS 3 4 3 4 WINDOWING 3 6 CHAPTER 4 STANDARD AND PTS INTERRUPTS 4 1 INTERRUPT SOURCES VECTORS AND PRIORITIES 4...

Page 4: ...5 8 3 1 4 Error Detection 8 5 8 3 2 Symbol Synchronization and Timing Circuitry 8 5 8 3 2 1 Clock Prescaler 8 6 8 3 2 2 Digital Filter 8 6 8 3 2 3 Delay Compensation 8 6 8 3 2 4 Symbol Encoding and D...

Page 5: ...1 IDENTIFYING THE RESET SOURCE 9 1 9 2 DESIGN CONSIDERATIONS FOR 8XC196LA LB AND LD 9 2 CHAPTER 10 SPECIAL OPERATING MODES 10 1 INTERNAL TIMING 10 1 10 2 ENTERING AND EXITING ONCE MODE 10 2 CHAPTER 11...

Page 6: ...7 4 7 4 EPA Interrupt Mask 1 EPA_MASK1 Register 7 4 7 5 EPA Interrupt Pending EPA_PEND Register 7 5 7 6 EPA Interrupt Pending 1 EPA_PEND1 Register 7 5 7 7 EPA Interrupt Priority Vector Register EPAIP...

Page 7: ...S FIGURES Figure Page 11 1 Slave Programming Circuit 11 3 11 2 Serial Port Programming Circuit 11 4 A 1 87C196LA 52 pin PLCC Package A 3 A 2 87C196LB 52 pin PLCC Package A 5 A 3 83C196LD 52 pin PLCC P...

Page 8: ...Interrupt Priority Vectors 7 6 8 1 J1850 Controller Signals 8 3 8 2 Control and Status Registers 8 3 8 3 Relationships Between Input Frequency PLL and Prescaler Bits 8 6 8 4 Huntzicker Symbol Timing C...

Page 9: ...1 Guide to This Manual...

Page 10: ......

Page 11: ...ters SFRs and provides tables of WSR values for windowing higher memory into the lower register file for direct access Chapter 4 Standard and PTS Interrupts describes the additional interrupts for the...

Page 12: ...cs with page number references 1 2 RELATED DOCUMENTS Table 1 1 lists additional documents that you may find useful in designing systems incorporating the 8XC196Lx microcontrollers Table 1 1 Related Do...

Page 13: ...2 Architectural Overview...

Page 14: ......

Page 15: ...sion applies to all the Kx Jx and CA controllers 2 1 MICROCONTROLLER FEATURES Table 2 1 lists the features of the 8XC196Lx and the 8XC196Kx Table 2 1 Features of the 8XC196Lx and 8XC196Kx Product Fami...

Page 16: ...plier or directly to the divide by two circuit The multiplier circuitry can double the input frequency FXTAL1 before the frequency f reaches the divide by two circuitry The clock generators accept the...

Page 17: ...uitry the signal on the CLKOUT pin is a delayed version of the internal CLKOUT signal This delay varies with temperature and voltage Phase locked Loop Clock Multiplier Phase Comparator Filter Phase lo...

Page 18: ...state times rather than specific measurements Datasheets list AC characteristics in terms of clock periods t sometimes called Tosc Figure 2 4 illustrates the timing relationships between the input fr...

Page 19: ...vides that frequency to produce the desired output frequency The CLK1 0 bits control the divisor divide f 2 by either 1 2 or 4 Table 2 3 Relationships Between Input Frequency Clock Multiplier and Sta...

Page 20: ...is sec tion provides a brief description of the peripherals that differ between the 8XC196Lx and the 8XC196Kx families USFR1 read only Address Reset State 1FF2H XXH The UPROM special function register...

Page 21: ...nnels 2 5 4 J1850 Communications Controller The 87C196LB microcontroller has a peripheral not found on the 8XC196Kx microcontrollers or any other Lx microcontroller the J1850 peripheral The J1850 comm...

Page 22: ......

Page 23: ...3 Address Space...

Page 24: ......

Page 25: ...F 2000 207F 2000 Special purpose memory internal nonvolatile or external memory Indirect or indexed 1FFF 1FE0 1FFF 1FE0 1FFF 1FE0 1FFF 1FE0 1FFF 1FE0 1FFF 1FE0 Memory mapped SFRs Indirect or indexed 1...

Page 26: ...tion from a location in the register file causes the memory controller to fetch the instruction from external memory 1BFF 0500 1BFF 0500 1BFF 0600 1BFF 0600 1BFF 0600 External device memory or I O con...

Page 27: ...001A 00FF 001A 00FF 001A 00FF 001A Lower register file register RAM Direct indirect or indexed 0019 0018 0019 0018 0019 0018 0019 0018 0019 0018 Lower register file stack pointer Direct indirect or in...

Page 28: ...served P0_PIN 1FF8H Reserved SLP_STAT 1FD8H Reserved Reserved 1FF6H P5_PIN USFR 1FD6H P6_PIN P1_PIN 1FF4H P5_REG P34_DRV 1FD4H P6_REG P1_REG 1FF2H P5_DIR USFR1 LA LB 1FD2H P6_DIR P1_DIR 1FF0H P5_MODE...

Page 29: ...PA1_CON L Address High Odd Byte Low Even Byte 1F62H EPA0_TIME H EPA0_TIME L 1FA8H Reserved EPAIPV 1F60H Reserved EPA0_CON 1FA6H Reserved EPA_PEND1 J1850 SFRs LB Only 1FA4H Reserved EPA_MASK1 Address H...

Page 30: ...alue for 64 byte Window 00C0 00FFH WSR Value for 128 byte Window 0080 00FFH Peripheral SFRs 1FE0H 7FH Note 3FH Note 1FH Note 1FC0H 7EH 1FA0H 7DH 3EH 1F80H 7CH 1F60H 7BH 3DH 1EH 1F40H 7AH 1F20H 79H 3CH...

Page 31: ...5H 02C0H 56H 02A0H 55H 2AH 0280H 54H 0260H 53H 29H 14H 0240H 52H 0220H 51H 28H 0200H 50H Upper Register File CA JR JT JV KR KT LA LB 01E0H 4FH 27H 13H 01C0H 4EH 01A0H 4DH 26H 0180H 4CH Table 3 4 Windo...

Page 32: ...ntinued Base Address WSR Value for 32 byte Window 00E0 00FFH WSR Value for 64 byte Window 00C0 00FFH WSR Value for 128 byte Window 0080 00FFH NOTE Locations 1FE0 1FFFH contain memory mapped SFRs that...

Page 33: ...4 Standard and PTS Interrupts...

Page 34: ......

Page 35: ...s that of the 8XC196Jx The only difference is that the slave port interrupts INT08 06 now support the J1850 controller peripheral 4 1 INTERRUPT SOURCES VECTORS AND PRIORITIES Table 4 1 lists the 8XC19...

Page 36: ...y J1850RX INT07 200EH 07 PTS07 204EH 22 Reserved LA LD INT07 200EH 07 PTS07 204EH 22 J1850 Transmit LB only J1850TX INT06 200CH 06 PTS06 204CH 21 Reserved LA LD INT06 200CH 06 PTS06 204CH 21 A D Conv...

Page 37: ...Number Function 7 0 Setting a bit enables the corresponding interrupt Bit Mnemonic Interrupt Description J1850RX J1850 Receive LB only J1850TX J1850 Transmit LB only AD A D Conversion Complete LA LB...

Page 38: ...7 0 LB NMI EXTINT RI TI SSIO1 SSIO0 J1850ST 7 0 LA LD NMI EXTINT RI TI SSIO1 SSIO0 Bit Number Function 7 0 Setting a bit enables the corresponding interrupt Bit Mnemonic Interrupt Description NMI Non...

Page 39: ...ing interrupt vector Bit Mnemonic Interrupt Description J1850RX J1850 Receive LB only J1850TX J1850 Transmit LB only AD A D Conversion Complete LA LB EPA0 EPA Capture Compare Channel 0 EPA1 EPA Captur...

Page 40: ...t pending bit 7 0 LB NMI EXTINT RI TI SSIO1 SSIO0 J1850ST 7 0 LA LD NMI EXTINT RI TI SSIO1 SSIO0 Bit Number Function 7 0 Any set bit indicates that the corresponding interrupt is pending The interrupt...

Page 41: ...14 0 Setting a bit causes the corresponding interrupt to be handled by a PTS microcode routine The PTS interrupt vector locations are as follows Bit Mnemonic Interrupt PTS Vector EXTINT EXTINT pin 20...

Page 42: ...an end of PTS interrupt for the corresponding interrupt through its standard interrupt vector The standard interrupt vector locations are as follows Bit Mnemonic Interrupt Standard Vector EXTINT EXTIN...

Page 43: ...5 I O Ports...

Page 44: ......

Page 45: ...gnals combine to drive the gates of Q1 and Q2 so that the output is high low or high impedance In special function mode selected by setting a port mode register bit SFDIR and SFDATA are input to the m...

Page 46: ...nctions The signals are latched into the port pin register sample latch and output onto the internal bus when the port pin register is read The falling edge of RESET turns on transistor Q3 which remai...

Page 47: ...ate either as a general purpose I O signal I O mode or as a special function signal special function mode In either mode three configurations are possible complementary output high Q2 Q1 Px_MODE Px_DR...

Page 48: ...put configurations In I O mode write the data that is to be driven by the pins to the corresponding Px_REG bits In special function mode the value is immaterial because the on chip peripheral or syste...

Page 49: ...ntrols the port through BUS CONTROL SELECT an internal control sig nal When the device needs to access external memory it clears BUS CONTROL SELECT selecting ADDRESS DATA as the input to the multiplex...

Page 50: ...e 87C196LA LB Only Q2 Q1 Px_REG P34_DRV Sample Latch PH1 Clock Internal Bus Address Data Px_PIN D Q Weak Pullup RESET Q3 Q4 Buffer Read Port LE 300ns Delay I O Pin Bus Control Select 0 Address Data 1...

Page 51: ...6 Synchronous Serial I O Port...

Page 52: ......

Page 53: ...mon clock signal for both SSIO channels 7 0 PHAS POLS Bit Number Bit Mnemonic Function 7 2 Reserved for compatibility with future devices write zeros to these bits 1 PHAS Phase and Polarity Select For...

Page 54: ...for channel 1 7 0 CHS DUP CONINT CONPND PHAS POLS Bit Number Bit Mnemonic Function 7 6 Reserved for compatibility with future devices write zeros to these bits 5 CHS These bits determine the SSIO oper...

Page 55: ...ng edges 0 1 high idle state shift on rising edges 1 0 low idle state shift on rising edges 1 1 high idle state shift on falling edges For receptions PHAS POLS 0 0 low idle state sample on rising edge...

Page 56: ......

Page 57: ...7 Event Processor Array...

Page 58: ......

Page 59: ...and without pins and compare only channels for each device in the 8XC196Lx and 8XC196Kx families The 8XC196Lx s EPA performs input and output functions associated with two timer counters timer 1 and t...

Page 60: ...errupt Processor Logic EPAx Interrupt A5269 01 Timer Counter Unit EPA9 COMP1 EPA8 COMP0 EPA 3 0 EPA 3 0 Interrupts TIMER1 TIMER2 Compare only Channel 1 Capture Compare Channel 9 Compare only Channel 0...

Page 61: ...m 83C196LD Only Indirect Interrupt Processor Logic EPAx Interrupt A5281 01 TIMER1 TIMER2 Timer Counter Unit Capture Compare Channel 9 Capture Compare Channel 8 Capture Compare Channel 6 7 Capture Comp...

Page 62: ...ster INT_MASK 0 1 Bits 2 5 and 14 15 are reserved on the 8XC196Lx device family For compatibility with future devices write zeros to these bits Figure 7 3 EPA Interrupt Mask EPA_MASK Register EPA_MASK...

Page 63: ...software reads the EPA interrupt priority vector register EPAIPV Bits 2 5 and 14 15 are reserved on the 8XC196Lx device family For compatibility with future devices write zeros to these bits Figure 7...

Page 64: ...EPAIPV When all the EPA pending bits are cleared the EPAx pending bit is also cleared 7 0 PV4 PV3 PV2 PV1 PV0 Bit Number Bit Mnemonic Function 5 7 Reserved for compatibility with future devices write...

Page 65: ...8 J1850 Communications Controller...

Page 66: ......

Page 67: ...ansfers messages between network nodes ac cording to the J1850 protocol The complete J1850 communications protocol solution includes an on chip J1850 digital logic controller working with an external...

Page 68: ...ircuitry six control and status registers transmit and receive buffers and an interrupt handler Figure 8 2 J1850 Communications Controller Block Diagram A5169 01 Peripheral Data Bus J_CFG J_CMD J_RX J...

Page 69: ...is register to determine the status of transmissions in progress J_DLY 1F58H J1850 Delay Compensation Program this byte register to define the length of the delay time through the external transceiver...

Page 70: ...ge On reception the calculated CRC checksum byte always results in a value of C4H for valid messages An invalid CRC check sum during reception signals the presence of an error in your incoming message...

Page 71: ...or the bus will continue to send their symbols until the next instance of contention is detected or arbitration is awarded This process continues until a complete message frame from one node has been...

Page 72: ...n 8 s and 34 s in duration is considered invalid and is flagged by the J_STAT register as a bus symbol timing error 8 3 2 3 Delay Compensation Because the digital portion of the J1850 protocol is inte...

Page 73: ...symbol establishes the priority for arbitration By definition an active bus level is a driven state and a passive bus level is a non driven or idle state A driven bus state is always given priority ov...

Page 74: ...over ruled by the driven state of the active 1 symbol on node A Thus node A is awarded arbitration The busline signal detected on the bus by the receiver reflects node A s message as this is the only...

Page 75: ...gineer ing SAE J1850 specifications revised May 1994 8 4 1 2 CRC Byte The CRC byte calculated through the cyclic redundancy check generator is a checksum value that verifies the accuracy of the data m...

Page 76: ...ol signals the end of the data transmission This is a passive level state symbol only It appears twice in IFR messaging at the end of the initial request data field and at the end of the IFR data fiel...

Page 77: ...ve 122 128 134 96 163 s Active 60 64 68 34 96 s Start of Frame SOF Active 193 200 207 163 239 s End of Data EOD Passive 193 200 207 163 239 s End of Frame EOF Passive 271 280 289 239 300 s In frame Se...

Page 78: ...f in formation from a single source in your system In the above example suppose you want to know how many pounds of pressure each of the four remote node sites experienced after the controller sent ou...

Page 79: ...receive messages in either standard or IFR form 8 5 1 Transmitting Messages To transmit a standard message prepare the message in register RAM and then write it to the J1850 transmit J_TX register Fi...

Page 80: ...in J_TX is automatically shifted into JTX_BUF freeing J_TX for another byte This process continues until the CSM has resolved the number of message bytes MSG3 0 programmed into the J_CMD register If t...

Page 81: ...for another byte Figure 8 15 Figure 8 15 J1850 Receive Message Structure After J_RX is read the byte residing in JRX_BUF is automatically shifted into J_RX freeing JRX_BUF for another reception This p...

Page 82: ...your system Refer to In frame Response Messaging on page 8 12 for a detailed explanation 8 6 PROGRAMMING THE J1850 CONTROLLER This section explains how to configure the J1850 controller Several regis...

Page 83: ...written to the J1850 transmitter J_TX register is an in frame response IFR 0 standard messaging 1 next byte written to J_TX is an IFR 5 IGNORE Ignore Incoming Message This bit instructs the bus to ig...

Page 84: ...on Bit Format This bit specifies which normalization bit NB format is to be used IFR with CRC Byte IFR without CRC Byte 0 active long NB 0 active short NB 1 active short NB 1 active long NB 6 IFR3 Typ...

Page 85: ...e bits ensure proper operation of the J1850 peripheral at the supported input frequencies FXTAL1 PRE1 PRE0 FXTAL1 0 0 8 MHz 0 1 12 MHz 1 0 16 MHz 1 1 20 MHz J_CFG Address Reset State 1F54H 00H The J18...

Page 86: ...byte register can be directly addressed through windowing 7 0 DLY4 DLY3 DLY2 DLY1 DLY0 Bit Number Bit Mnemonic Function 7 5 Reserved for compatibility with future devices write zeros to these bits 4...

Page 87: ...s whether the IFR byte has been received and is ready to be read from the J1850 receiver J_RX register 0 no action 1 IFR byte received 6 BUS_CONT J1850 Bus Contention This bit indicates whether bus co...

Page 88: ...e is received on the bus an invalid bus symbol is detected on the bus a transmission occurs and the feedback through the receiver is not detected within 60 s J_STAT Address Reset State 1F53H 00H The J...

Page 89: ...9 Minimum Hardware Considerations...

Page 90: ......

Page 91: ...the microcontroller encountered 7 0 CFDRST WDTRST SFWRST EXTRST Bit Number Bit Mnemonic Function 7 4 Reserved for compatibility with future devices write zeros to these bits 3 CFDRST Clock Failure De...

Page 92: ...Slave port Since the 8XC196Lx has no P5 1 SLPCS and P5 4 SLPINT pins you cannot use the slave port ONCE mode On the 8XC196Lx the ONCE mode entry function is multiplexed with P2 6 and TXJ1850 on the 87...

Page 93: ...10 Special Operating Modes...

Page 94: ......

Page 95: ...ircuit emulation ONCE special purpose mode op eration has changed slightly because of the new reset state pin levels that have been implemented 10 1 INTERNAL TIMING The 87C196LA and LB clock circuitry...

Page 96: ...as changed from a weak logic 1 wk1 to a weak logic 0 wk0 ONCE shares a package with port pin 2 6 Asserting and holding the ONCE signal high during the rising edge of RESET causes the device to enter O...

Page 97: ...AL OPERATING MODES an output If you choose to configure this pin as an input always hold it low during reset and en sure that your system meets the VIH specification to prevent inadvertent entry into...

Page 98: ......

Page 99: ...11 Programming the Nonvolatile Memory...

Page 100: ......

Page 101: ...cuits for the 87C196LA and LB 11 1 SIGNATURE WORD AND PROGRAMMING VOLTAGE VALUES The 8XC196Lx s programming voltage values are the same as those of the 8XC196Kx however the signature word value diffe...

Page 102: ...040 PTS vectors 203F 2030 Upper interrupt vectors 202F 2020 Security key 201F 201C Reserved each location must contain FFH 201B Reserved must contain 20H 201A CCB1 2019 Reserved must contain 20H 2018...

Page 103: ...ng VCC 0072H Read Only Programming VPP 0073H Read Only Signature word 0070H Read Only These bits program the UPROM cells Once these bits are programmed they cannot be erased and dynamic failure analys...

Page 104: ...map for serial port programming Figure 11 2 Serial Port Programming Circuit 5 9 4 8 3 7 2 6 1 1 8k 1 8k 1 8k 1 8k 1 8k 10 F A5278 01 RXD TXD RXD TXD VCC 87C196LA LB 30 pF 30 pF XTAL1 XTAL2 P0 7 PMODE...

Page 105: ...ble 11 4 Serial Port Programming Mode Address Map Description Address Range Normal Operation Serial Port Programming Mode Internal OTPROM 2000 7FFFH A000 FFFFH External memory 4000 9FFFH Do not addres...

Page 106: ......

Page 107: ...A Signal Descriptions...

Page 108: ......

Page 109: ...ation for the pin functions of the 8XC196Lx microcon trollers A 1 FUNCTIONAL GROUPINGS OF SIGNALS Tables A 1 A 2 and A 3 list the signal assignments for the 8XC196Lx microcontrollers grouped by functi...

Page 110: ...18 PBUS 5 17 ADV ALE 2 AD10 12 P3 5 17 PBUS 6 16 CLKOUT 32 AD11 11 P3 6 16 PBUS 7 15 RD 5 AD12 10 P3 7 15 PBUS 8 14 WR WRL 6 AD13 9 P4 0 14 PBUS 9 13 AD14 8 P4 1 13 PBUS 10 12 Power Ground AD15 7 P4 2...

Page 111: ...AD13 P4 5 PBUS 13 AD12 P4 4 PBUS 12 AD11 P4 3 PBUS 11 AD10 P4 2 PBUS 10 AD9 P4 1 PBUS 9 AD8 P4 0 PBUS 8 AD7 P3 7 PBUS 7 AD6 P3 6 PBUS 6 AD5 P3 5 PBUS 5 AD4 P3 4 PBUS 4 AD3 P3 3 PBUS 3 AD2 P3 2 PBUS 2...

Page 112: ...13 P3 4 18 PBUS 5 17 ADV ALE 2 AD10 12 P3 5 17 PBUS 6 16 CLKOUT 32 AD11 11 P3 6 16 PBUS 7 15 RD 5 AD12 10 P3 7 15 PBUS 8 14 WR WRL 6 AD13 9 P4 0 14 PBUS 9 13 AD14 8 P4 1 13 PBUS 10 12 Power Ground AD1...

Page 113: ...4 5 PBUS 13 AD12 P4 4 PBUS 12 AD11 P4 3 PBUS 11 AD10 P4 2 PBUS 10 AD9 P4 1 PBUS 9 AD8 P4 0 PBUS 8 AD7 P3 7 PBUS 7 AD6 P3 6 PBUS 6 AD5 P3 5 PBUS 5 AD4 P3 4 PBUS 4 AD3 P3 3 PBUS 3 AD2 P3 2 PBUS 2 46 45...

Page 114: ...18 P2 0 TXD 27 P6 0 EPA8 45 RESET 23 AD5 17 P2 1 RXD 28 P6 1 EPA9 46 XTAL1 52 AD6 16 P2 2 29 P6 4 SC0 47 XTAL2 51 AD7 15 P2 4 30 P6 5 SD0 48 AD8 14 P2 6 31 P6 6 SC1 49 Bus Control Status AD9 13 P2 7 3...

Page 115: ...n LoZ0 Low impedance strongly driven low WK1 Weak pull up LoZ1 Low impedance strongly driven high ODIO Open drain I O A3403 02 P6 1 EPA9 P6 0 EPA8 P1 0 EPA0 T2CLK P1 1 EPA1 P1 2 EPA2 T2DIR P1 3 EPA3 V...

Page 116: ...Note 1 P5 3 RD WK0 WK0 Note 1 Note 1 P6 0 EPA8 COMP0 WK0 WK0 Note 1 Note 1 P6 1 EPA9 COMP1 WK0 WK0 Note 1 Note 1 P6 4 SC0 WK0 WK0 Note 1 Note 1 P6 5 SD0 WK0 WK0 Note 1 Note 1 P6 6 SC1 WK0 WK0 Note 1 N...

Page 117: ...WK1 WK1 Note 1 Note 1 P6 0 EPA8 WK1 WK1 Note 1 Note 1 P6 1 EPA9 WK1 WK1 Note 1 Note 1 P6 4 SC0 WK1 WK1 Note 1 Note 1 P6 5 SD0 WK1 WK1 Note 1 Note 1 P6 6 SC1 WK1 WK1 Note 1 Note 1 P6 7 SD1 WK1 WK1 Note...

Page 118: ......

Page 119: ...Glossary...

Page 120: ......

Page 121: ...erts an analog input to a digital value ALU Arithmetic logic unit The part of the RALU that processes arithmetic and logical operations assert The act of making a signal active enabled The polarity hi...

Page 122: ...ne multiplexer channel to another characteristic A graph of output code versus input voltage the transfer function of an A D converter chip select unit The integrated module that selects an external m...

Page 123: ...al nonlinearity The difference between the actual code width and the ideal one LSB code width of the terminal based characteristic of an A D converter It provides a measure of how much the input volta...

Page 124: ...oltage corresponding to the final full scale code transition of an A D converter hold latency The time it takes the microcontroller to assert HLDA after an external device asserts HOLD ideal character...

Page 125: ...ne A software routine that you provide to service a standard interrupt request interrupt vector A location in special purpose memory that holds the starting address of an interrupt service routine J18...

Page 126: ...it nonmonotonic behavior MSB Most significant bit of a byte or most significant byte of a word MSW Most significant word of a double word or quad word multiplexed bus The configuration in which the mi...

Page 127: ...stor with a p type conducting path p type material Semiconductor material with introduced impurities doping causing it to have an excess of positively charged carriers PC Program counter phase locked...

Page 128: ...at reflect the state of the current program The low byte of the PSW is the INT_MASK register A PUSHA or POPA instruction saves or restores both bytes PSW INT_MASK a PUSHF or POPF saves or restores onl...

Page 129: ...ltage and frequency conditions The amount of repeatability error depends on the comparator s ability to resolve very similar voltages and the extent to which random noise contributes to the error rese...

Page 130: ...RESET is a level sensitive input EXTINT is normally a sampled input however the powerdown circuitry uses EXTINT as a level sensitive input during powerdown mode SAR Successive approximation register A...

Page 131: ...variable for each degree Centigrade of temperature change temperature drift The change in a specification due to a change in temperature Temperature drift can be calculated by using the temperature co...

Page 132: ...ernal bus cycles to allow a slow memory device to respond to a request from the microcontroller watchdog timer An internal timer that resets the microcontroller if software fails to respond before the...

Page 133: ...Index...

Page 134: ......

Page 135: ...register 7 5 interrupt priority vector register 7 6 ESD protection 5 2 5 5 F Formulas clock period t 2 4 PH1 and PH2 frequency 2 4 state time 2 4 Frequency f 2 4 FXTAL1 2 4 H Hardware pin reset status...

Page 136: ...status A 8 A 9 Register file and windowing 3 2 description 3 3 Registers EPA_MASK 7 4 EPA_MASK1 7 4 EPA_PEND 7 5 EPA_PEND1 7 5 EPAIPV 7 6 INT_MASK 4 3 INT_MASK1 4 4 INT_PEND 4 5 INT_PEND1 4 6 J_CFG 8...

Reviews:

No comments

Brands by name

Popular brands

Load more brands