Intel 87C196CA, Supplement To User’S Manual

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8XC196L
X SUPPLEMENT
8-22
2 MSG_TX Message Transmit Interrupt
This bit signals the successful transmission of a message upon detecting
the EOD symbol.
0 = no action
1 = message transmitted
1 MSG_RX Message Receive Interrupt
This bit signals the successful reception of a message upon detecting the
EOD symbol.
0 = no action
1 = message received
0 J1850BE J1850 Bus Error Interrupt
This bit is set if one or more of the following conditions occur:
• the calculated CRC for a received message does not equal C4H
• an incomplete byte is received on the bus
• an invalid bus symbol is detected on the bus
• a transmission occurs and the feedback through the receiver is not
detected within 60 µs
J_STAT
Address:
Reset State:
1F53H
00H
The J1850 status (J_STAT) register provides the current status of the message transfer, the receive
and transmit buffers, and the four interrupt sources associated with the J1850 protocol. This byte
register can be directly addressed through
windowing. You must write to this register before
transmitting each message. Reading this register clears all bits except BUS_STAT.
7 0
IFR_RCV BUS_CONT BUS_STAT BRK_RCV OVR_UNDR MSG_TX MSG_RX J1850BE
Bit
Number
Bit
Mnemonic
Function
Figure 8-19. J1850 Status (J_STAT) Register (Continued)