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Glossary-3
GLOSSARY
contention
The detection of conflicting symbols or bits on the
bus.
crosstalk See
off-isolation.
DC input leakage
Leakage current from an analog input pin to ground or
to the reference voltage (V
REF
).
deassert
The act of making a signal inactive (disabled). The
polarity (high or low) is defined by the signal name.
Active-low signals are designated by a pound symbol
(#) suffix; active-high signals have no suffix. To
deassert RD# is to drive it high; to deassert ALE is to
drive it low.
demultiplexed bus
The configuration in which the microcontroller uses
separate lines for address and data (address on A20:0;
data on AD15:0 for a 16-bit bus or AD7:0 for an 8-bit
bus). See also multiplexed bus.
differential nonlinearity
The difference between the actual code width and the
ideal one-LSB code width of the terminal-based
characteristic of an A/D converter. It provides a
measure of how much the input voltage may have
changed in order to produce a one-count change in the
conversion result. Differential nonlinearity is a
measure of local code-width error; nonlinearity is a
measure of overall code-transition error.
doping
The process of introducing a periodic table Group III
or Group V element into a Group IV element (e.g.,
silicon). A Group III impurity (e.g., indium or
gallium) results in a p-type material. A Group V
impurity (e.g., arsenic or antimony) results in an n-
type material.
double-word
Any 32-bit unit of data.
DOUBLE-WORD
An unsigned, 32-bit variable with values from 0
through 2
32
–1.
EPA
Event processor array. An integrated peripheral that
provides high-speed input/output capability.
ESD
Electrostatic discharge.
Summary of Contents for 87C196CA
Page 9: ...1 Guide to This Manual...
Page 10: ......
Page 13: ...2 Architectural Overview...
Page 14: ......
Page 22: ......
Page 23: ...3 Address Space...
Page 24: ......
Page 33: ...4 Standard and PTS Interrupts...
Page 34: ......
Page 43: ...5 I O Ports...
Page 44: ......
Page 51: ...6 Synchronous Serial I O Port...
Page 52: ......
Page 56: ......
Page 57: ...7 Event Processor Array...
Page 58: ......
Page 65: ...8 J1850 Communications Controller...
Page 66: ......
Page 89: ...9 Minimum Hardware Considerations...
Page 90: ......
Page 93: ...10 Special Operating Modes...
Page 94: ......
Page 98: ......
Page 99: ...11 Programming the Nonvolatile Memory...
Page 100: ......
Page 106: ......
Page 107: ...A Signal Descriptions...
Page 108: ......
Page 118: ......
Page 119: ...Glossary...
Page 120: ......
Page 133: ...Index...
Page 134: ......